A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication Techniques

建议没有。题目：一种利用超宽带和无线通信技术进行可测试性设计（DFT）的新方法。机构：弗吉尼亚理工学院和州立大学摘要IC中的配电网络是普遍存在的，从内部逻辑来看，即电力线可以被任何内部节点访问。这表明通过电源线监测或控制任何内部节点的逻辑值的可能性，只需在节点上附加一个简单且几乎全数字的传感/控制电路。换句话说，IC中的电力线通信（PLC）为设计人员提供了访问内部节点的廉价手段，可用于各种应用，包括减少扫描设计，系统调试，故障诊断，内置自检期间监测瞬态逻辑值的测试应用时间，以及在线测试。本研究以电路测试为主要目标应用，探讨了PLC在集成电路中的可行性和实用性。项目成功实施后，主要技术成果如下：(1)提出了解决超大规模集成电路测试问题的新方法；(2)探索了一个新的领域——集成电路级PLC；(3)在IC级开发PLC所需的构建模块。电力线在IC级的使用以前从未被探索过，它在VLSI测试和其他领域（如片内/片间级通信）提供了大量的新应用。这项研究的结果将发表在期刊和会议记录上，并将在技术会议上提出。建议进行的研究亦会促进研究与教育的结合，并会用于改善理大的课程。年代的机构。这个项目提供了一个很好的机会，培养本科生和代表性不足的学生在各种电气工程领域，包括VLSI测试，模拟和混合信号设计，RFIC设计，以及电路和系统级仿真。该项研究的初步可行性研究已与一家美国主要半导体公司密切合作进行，其他几家美国半导体公司也已承诺在这项研究中进行合作。与这些公司的密切合作将在项目成功结束时为研究的商业化提供一条直接途径。

Proposal No.: 811706PI: Ha, Dong S.Title: A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication TechniquesInstitution: Virginia Polytechnic Institute and State UniversityABSTRACTA power distribution network in an IC is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple and nearly all-digital sensing/control circuit to the node. In other words, power line communications (PLC) in an IC provides designers with an inexpensive means to access to internal nodes, which can be useful for various applications, including test application time reduction for scan design, system debugging, fault diagnosis, monitoring transient logic values during built-in self test, and on-line testing. The research investigates the feasibility and practicality of PLC in ICs with circuit testing as the major target application. Upon successful execution of the project, the major technical accomplishments are as follows. (1) it suggests a new approach to address VLSI testing problems; (2) it investigates a new area, PLC at the IC level; and (3) it develops the necessary building blocks for PLC at the IC level. The use of power lines at the IC level has not been explored before, and it offers vast new applications in VLSI testing and other areas such as intra-/inter- chip level communications.The outcomes of this research will be published in journals and proceedings and will be presented at technical conferences. The proposed research will also foster the integration of research and education and will be used to enhance the curriculum at the PI?s institution. This project provides an excellent opportunity to train undergraduate and underrepresented students in various electrical engineering fields, including VLSI testing, analog and mixed signal design, RFIC design, and circuit and system level simulation. An initial feasibility study for the proposed research has been conducted in close collaboration with a major US semiconductor company, and several other US semiconductor companies also have committed to collaborate in the proposed research. Close collaboration with those companies will provide a direct path to commercialization of the research at the successful conclusion of the project.