A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication Techniques

方案编号：811706 PI：Ha，Dong S.Title：利用超宽带和无线通信技术实现可测性设计的新方法研究机构：弗吉尼亚理工学院和州立大学摘要集成电路中的配电网络从内部逻辑上看是无处不在的，即，电力线可接入任何内部节点。这表明通过将简单且几乎全数字的感测/控制电路附接到节点来通过电力线监视或控制任何内部节点的逻辑值的可能性。换句话说，IC中的电力线通信（PLC）为设计者提供了访问内部节点的廉价手段，这可用于各种应用，包括用于扫描设计的测试应用时间减少、系统调试、故障诊断、在内建自测试期间监视瞬态逻辑值以及在线测试。本研究以电路测试为主要应用对象，探讨PLC在积体电路中的可行性与实用性。项目成功实施后，主要技术成果如下。(1)它提出了一种新的方法来解决超大规模集成电路测试问题; 2（2）它调查了一个新的领域，在IC级的PLC; 3（3）它开发了必要的积木PLC在IC级。电源线在集成电路层面的使用以前从未被探索过，它在超大规模集成电路测试和其他领域（如芯片内/芯片间通信）提供了大量新的应用。这项研究的成果将发表在期刊和会议录上，并将在技术会议上发表。拟议的研究还将促进研究和教育的整合，并将用于提高PI？的制度。该项目提供了一个很好的机会，培养本科生和代表性不足的学生在各个电气工程领域，包括VLSI测试，模拟和混合信号设计，RFIC设计，电路和系统级仿真。该研究的初步可行性研究已与美国一家主要半导体公司密切合作进行，其他几家美国半导体公司也承诺在拟议的研究中进行合作。与这些公司的密切合作将为该项目的成功结束提供一条将研究商业化的直接途径。

Proposal No.: 811706PI: Ha, Dong S.Title: A New Approach to Design-for-Testability (DFT) Using Ultra Wideband and Wireless Communication TechniquesInstitution: Virginia Polytechnic Institute and State UniversityABSTRACTA power distribution network in an IC is ubiquitous as seen by the internal logic, i.e., a power line is accessible to any internal node. This suggests the possibility of monitoring or controlling the logic value of any internal node through a power line by attaching a simple and nearly all-digital sensing/control circuit to the node. In other words, power line communications (PLC) in an IC provides designers with an inexpensive means to access to internal nodes, which can be useful for various applications, including test application time reduction for scan design, system debugging, fault diagnosis, monitoring transient logic values during built-in self test, and on-line testing. The research investigates the feasibility and practicality of PLC in ICs with circuit testing as the major target application. Upon successful execution of the project, the major technical accomplishments are as follows. (1) it suggests a new approach to address VLSI testing problems; (2) it investigates a new area, PLC at the IC level; and (3) it develops the necessary building blocks for PLC at the IC level. The use of power lines at the IC level has not been explored before, and it offers vast new applications in VLSI testing and other areas such as intra-/inter- chip level communications.The outcomes of this research will be published in journals and proceedings and will be presented at technical conferences. The proposed research will also foster the integration of research and education and will be used to enhance the curriculum at the PI?s institution. This project provides an excellent opportunity to train undergraduate and underrepresented students in various electrical engineering fields, including VLSI testing, analog and mixed signal design, RFIC design, and circuit and system level simulation. An initial feasibility study for the proposed research has been conducted in close collaboration with a major US semiconductor company, and several other US semiconductor companies also have committed to collaborate in the proposed research. Close collaboration with those companies will provide a direct path to commercialization of the research at the successful conclusion of the project.