Bi-Level Reconfigurations of Fault Tolerant Arrays in Bi- Modal Computational Environments

双模计算环境中容错阵列的双层重构

• 批准号: 8911303
• 负责人: Rami Melhem
• 金额: $ 6.15万
• 依托单位: University of Pittsburgh
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1989
• 资助国家: 美国
• 起止时间: 1989-09-01 至 1992-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=8911303&HistoricalAwards=false
• 关键词: Bi; Level; Reconfigurations; Fault; Tolerant

The objective of this research is on developing fault-tolerant architectures and algorithms for processor arrays. The computational loads of these systems are assumed to alternate between two phases: a strict phase that is characterized by a heavy load and strict constraints on response time, and a relaxed phase that is characterized by a light load and relatively relaxed constraints on response time. Under this type of load, a bi-level algorithm is applied to reconfigure the system after faults. Specifically, at one level, called the fast response level, a local distributed fault-tolerant algorithm is used during strict phases to achieve fast fault recovery at the expense of possible rapid degradation in the potential to tolerate future faults. To minimize the effect of this degradation, a second level, called the optimization level, uses a relatively slow reorganization algorithm during relaxed phases to restore the system into a state that ensures adequate fault tolerance in the remaining part of the system's mission. Computing arrays provide computational power that is comparable to that of supercomputers. Fault tolerance of these arrays is a very important issue. Traditional approaches focus on reconfiguring a faulty processor with a fixed local pool of spares. This inflexibility reduces the fault coverage capability and thus the reliability of the entire system. The approach studied in this research considers two types of algorithms: local algorithms and global algorithms. Local algorithms reconfigure faulty processors using local information, while global algorithms optimizes redundancy according to some fault tolerance criteria. A combination of these two types of algorithms allow a better tradeoff in fault tolerance of the overall system.

本研究的目标是开发容错 处理器阵列的架构和算法。 计算 假设这些系统的负荷在两个阶段之间交替： 严格的阶段，其特征在于负载重且严格 对响应时间的限制，以及一个宽松的阶段，其特征是 通过轻负载和相对宽松的响应时间约束。 在这种类型的负载下，应用双层算法来重新配置 故障后的系统。 具体来说，在一个层面上， 响应级，采用局部分布式容错算法 在严格的阶段，以实现快速故障恢复，代价是 容忍未来故障的潜力可能迅速下降。 为了最小化这种降级的影响，第二个级别称为 优化级别，使用相对较慢的重组算法 在放松阶段，将系统恢复到确保 在系统的使命的剩余部分中具有足够的容错能力。 计算阵列提供的计算能力可与 超级计算机。 这些阵列的容错性非常重要 问题. 传统的方法侧重于重新配置一个有缺陷的 具有固定的本地备用池的处理器。 这种不灵活性 降低了故障覆盖能力，从而降低了 整个系统。 本研究中研究的方法考虑了两个 算法类型：局部算法和全局算法。 当地 算法使用本地信息重新配置故障处理器， 全局算法根据故障情况优化冗余度 公差标准。 这两种算法的组合 允许在整个系统的容错性方面更好的折衷。