Bi-Level Reconfigurations of Fault Tolerant Arrays in Bi- Modal Computational Environments

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The objective of this research is on developing fault-tolerant architectures and algorithms for processor arrays. The computational loads of these systems are assumed to alternate between two phases: a strict phase that is characterized by a heavy load and strict constraints on response time, and a relaxed phase that is characterized by a light load and relatively relaxed constraints on response time. Under this type of load, a bi-level algorithm is applied to reconfigure the system after faults. Specifically, at one level, called the fast response level, a local distributed fault-tolerant algorithm is used during strict phases to achieve fast fault recovery at the expense of possible rapid degradation in the potential to tolerate future faults. To minimize the effect of this degradation, a second level, called the optimization level, uses a relatively slow reorganization algorithm during relaxed phases to restore the system into a state that ensures adequate fault tolerance in the remaining part of the system's mission. Computing arrays provide computational power that is comparable to that of supercomputers. Fault tolerance of these arrays is a very important issue. Traditional approaches focus on reconfiguring a faulty processor with a fixed local pool of spares. This inflexibility reduces the fault coverage capability and thus the reliability of the entire system. The approach studied in this research considers two types of algorithms: local algorithms and global algorithms. Local algorithms reconfigure faulty processors using local information, while global algorithms optimizes redundancy according to some fault tolerance criteria. A combination of these two types of algorithms allow a better tradeoff in fault tolerance of the overall system.