Performance-Driven Layout

本研究是在放置过程中统一考虑时间和几何约束的方法。该方法是使用“定义窗口”将时间约束转换为几何形状。窗口表示沿给定路径放置所有模块而不会降低电路性能的区域。然后，根据窗口信息，采用建设性放置过程选择未放置的模块，并为模块找到合适的位置。目前正在研究的算法包括：路径消除、窗口和区域构建、模块选择、模块放置和路径分割、松弛分布。

This research is on a unified way to consider both timing and geometric constraints during the placement process. The approach is to convert timing constraints to geometric shapes using "defined windows". A window represents a region in which all the modules along a given path can be placed without degrading the circuit performance. Then, based on the window information, a constructive placement process is used to select an unplaced module and to find an appropriate position for the module. Algorithms for the following issues are being studied: path elimination, window and region construction, module selection, module placement and path breaking, and slack distribution.