Performance Driven Layout and Logic Synthesis

性能驱动布局和逻辑综合

• 批准号: 0098069
• 负责人: Malgorzata Marek-Sadowska
• 金额: $ 35.06万
• 依托单位: University of California-Santa Barbara
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-09-01 至 2005-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0098069&HistoricalAwards=false
• 关键词: Performance; Driven; Layout; Logic; Synthesis

The increased chip complexity causes that average interconnect lengths increase and proportionallylarger and larger fraction of chip's area is occupied by interconnects. This proposal addresses several is-suesrelated to interconnects in submicron technologies.We will concentrate on simultaneous switching cross-talk noise effects in RC interconnects. Our goalhere is to develop efficient, easy to compute and accurate bounds on delay in the presence of crosstalk andto characterize and prevent propagating crosstalk signals. Besides correcting the crosstalk caused prob-lemswe will also develop methodologies of circuit optimization in the presence of crosstalk. We will developgate sizing tool, buffer insertion, spacing and net reordering which will consider both cross-talk and delay.At the same time we will explore regularity at the Boolean level to achieve layouts with mostly localinterconnects. The ultimate goal is to develop logic synthesis methodology which would produce highly reg-ular layout structures without large area penalty. We propose to continue our work on wave steered design methodology and we will develop tools for logic synthesis and physical design of such circuits.

芯片复杂性的增加导致平均互连长度的增加，并且互连所占芯片面积的比例越来越大。该提案解决了与亚微米技术中互连相关的几个问题。我们将集中讨论RC互连中的同步开关串扰噪声效应。我们的目标是在串扰存在的情况下开发高效、易于计算和准确的延迟边界，并表征和防止串扰信号的传播。除了纠正串扰引起的问题外，我们还将开发串扰存在下的电路优化方法。我们将开发大小工具，缓冲区插入，间距和网络重新排序，将考虑串扰和延迟。同时，我们将探索布尔级别的规则性，以实现大多数局部互连的布局。最终目标是发展逻辑综合方法，使其产生高度规则的布局结构，而不会造成大面积的损失。我们建议继续研究波控设计方法，我们将开发用于这种电路的逻辑合成和物理设计的工具。