Manufacturability-aware performance-driven layout-centric design automation of analog and RF integrated circuits

由于对相关模拟/射频效应的高灵敏度以及模拟/射频计算机辅助设计（CAD）工具的有限可用性，模拟/射频电路已被认为是将片上系统产品推向市场的设计瓶颈。特别是，到目前为止，大多数模拟/RF布局必须由电路设计师手工制作。因此，与布图相关的约束很难被满足并包含在电路综合中。在本提案中，提出了在深亚微米和纳米技术中开发模拟/射频集成电路的鲁棒电路/布局合成的设计方法和CAD工具。这项工作将集中在建立完整的电路合成流程，研究性能驱动的自动布局生成，充分考虑先进技术中不同的可制造性问题，以及探索电路调谐辅助的布局自动化。这将是模拟/射频集成电路第一个完全自动化的可制造性感知性能驱动的以布局为中心的合成方法。在电路合成流程中，集成了布局自动化。电路调谐考虑到与布局相关的影响，因此电路拓扑和大小可以被细化。本文提出的完整版面设计流程由自动模板生成和基于模板的压缩两部分组成。我们将基于宏单元布局方法开发一种新的基于模板的方案，以促进知识产权的重用。因此，在不影响设计效率的情况下，生成的布局在性能和可制造性方面是可靠的。

Analog/RF circuits have been recognized as the design bottleneck for getting System-on-Chip products to market due to the high sensitivity to the associated analog/RF effects and the limited availability of analog/RF computer-aided design (CAD) tools. In particular, so far most of analog/RF layouts have to be handcrafted by circuit designers. Thus, the layout-related constraints are hard to be satisfied and included in the circuit synthesis. In this proposal, the development of design methodology and CAD tools for robust circuit/layout synthesis of analog/RF integrated circuits in deep-submicron and nano technologies is proposed. This work will focus on setting up complete circuit synthesis flow, investigating performance-driven automatic layout generation, fully taking into account distinct manufacturability issues in the advanced technologies, and exploring layout automation aided by circuit tuning. This will be the first fully automated manufacturability- aware performance-driven layout-centric synthesis methodology for analog/RF integrated circuits. In the circuit synthesis flow, the layout automation is integrated. Circuit tuning takes into account the layout-related effects so that circuit topology and sizing can be refined. The proposed complete layout design flow is composed of automatic template generation and template-based compaction. We will develop a new template-based scheme based on the macro-cell layout approach to facilitate the intellectual property reuse. Thus, the generated layout is reliable in the sense of performance and manufacturability without compromising the design efficiency.