Manufacturability-aware performance-driven layout-centric design automation of analog and RF integrated circuits

模拟/射频电路已经被认为是将片上系统产品推向市场的设计瓶颈，因为它对相关的模拟/射频效应非常敏感，而且模拟/射频计算机辅助设计(CAD)工具的可用性有限。特别是，到目前为止，大多数模拟/射频布局都必须由电路设计人员手工制作。因此，与版图相关的约束很难得到满足，并被包含在电路综合中。在该方案中，提出了用于深亚微米和纳米技术的模拟/射频集成电路的稳健电路/版图综合的设计方法和CAD工具的发展。这项工作将集中于建立完整的电路综合流程，研究以性能为导向的版图自动生成，充分考虑先进技术中不同的可制造性问题，并探索辅助电路调整的版图自动化。这将是模拟/射频集成电路的第一个全自动化、可制造性感知、性能驱动、以布局为中心的综合方法。在电路综合流程中，集成了版图自动化。电路调整考虑了与布局相关的影响，因此可以改进电路拓扑和大小。所提出的完整布局设计流程由模板自动生成和基于模板的压缩两部分组成。我们将开发一种基于宏单元布局方法的基于模板的新方案，以促进知识产权重用。因此，在不影响设计效率的情况下，生成的布局在性能和可制造性方面是可靠的。

Analog/RF circuits have been recognized as the design bottleneck for getting System-on-Chip products to market due to the high sensitivity to the associated analog/RF effects and the limited availability of analog/RF computer-aided design (CAD) tools. In particular, so far most of analog/RF layouts have to be handcrafted by circuit designers. Thus, the layout-related constraints are hard to be satisfied and included in the circuit synthesis. In this proposal, the development of design methodology and CAD tools for robust circuit/layout synthesis of analog/RF integrated circuits in deep-submicron and nano technologies is proposed. This work will focus on setting up complete circuit synthesis flow, investigating performance-driven automatic layout generation, fully taking into account distinct manufacturability issues in the advanced technologies, and exploring layout automation aided by circuit tuning. This will be the first fully automated manufacturability- aware performance-driven layout-centric synthesis methodology for analog/RF integrated circuits. In the circuit synthesis flow, the layout automation is integrated. Circuit tuning takes into account the layout-related effects so that circuit topology and sizing can be refined. The proposed complete layout design flow is composed of automatic template generation and template-based compaction. We will develop a new template-based scheme based on the macro-cell layout approach to facilitate the intellectual property reuse. Thus, the generated layout is reliable in the sense of performance and manufacturability without compromising the design efficiency.