Manufacturability-aware performance-driven layout-centric design automation of analog and RF integrated circuits

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Analog/RF circuits have been recognized as the design bottleneck for getting System-on-Chip products to market due to the high sensitivity to the associated analog/RF effects and the limited availability of analog/RF computer-aided design (CAD) tools. In particular, so far most of analog/RF layouts have to be handcrafted by circuit designers. Thus, the layout-related constraints are hard to be satisfied and included in the circuit synthesis. In this proposal, the development of design methodology and CAD tools for robust circuit/layout synthesis of analog/RF integrated circuits in deep-submicron and nano technologies is proposed. This work will focus on setting up complete circuit synthesis flow, investigating performance-driven automatic layout generation, fully taking into account distinct manufacturability issues in the advanced technologies, and exploring layout automation aided by circuit tuning. This will be the first fully automated manufacturability- aware performance-driven layout-centric synthesis methodology for analog/RF integrated circuits. In the circuit synthesis flow, the layout automation is integrated. Circuit tuning takes into account the layout-related effects so that circuit topology and sizing can be refined. The proposed complete layout design flow is composed of automatic template generation and template-based compaction. We will develop a new template-based scheme based on the macro-cell layout approach to facilitate the intellectual property reuse. Thus, the generated layout is reliable in the sense of performance and manufacturability without compromising the design efficiency.        Having attracted strong interest in academia and industry, the circuit/layout design automation of analog/RF integrated circuits has enormous potential for commercialization. This proposed research work addresses the increasingly serious performance and manufacturability problems for analog/RF integrated circuits in deep-submicron and nano technologies. It will benefit analog/RF designers by significantly improving the design efficiency and reliability. This research program would enhance the competitive ability of Canada in this field.