Workshop on Packaging, Interconnects, Optoelectronics for the Design of Parallel Computers; March 18-19, 1992; Schaumburg, Illinois

该奖项提供了部分资金，为一个研讨会，以访问 目前最先进的实施高 性能并行机。 用于大型高速并联 系统，计算机设计师面临的问题必须是 从体系结构和互连两方面解决 perspective. 机器和包装工程师必须协同工作 为了识别和解决与时钟有关的问题， 在硬件布局之前进行分布、布线和分区 完成了 互连和封装对并行性的影响 和时钟速度进行评估。 此外，研讨会还讨论了 课题涉及电路板、芯片面积限制、信号 退化，电磁建模和仿真 互连、CAD模拟、光计算及其影响 机器性能。 研讨会领域包括微电子 包装、光电子、机器架构、处理器设计、 VLSI和CAD，主题分为三个领域之一：（1） 电子封装和互连;（2）光电子和 光学技术;（3）机器结构。

This award provides partial funding for a workshop to access current state-of-the-art schemes for implementation of high- performance parallel machines. For large high-speed parallel systems, the problems facing the computer designer must be addressed from both the architecture and the interconnection perspective. Machine and packaging engineers must work in concert in order to identify and solve the issues pertaining to clock distribution, routing, and partitioning before the hardware layout is done. The effects of interconnects and packaging on parallelism and clock speed are evaluated. Also, the workshop addresses subjects related to board, chip area constraints, signal degradation, electromagnetic modeling and simulation of interconnects, CAD simulation, optical computing, and their effect on machine performance. Workshop areas include microelectronics packaging, optoelectronics, machine architecture, processor design, VLSI, and CAD with topics grouped into one of three areas: (1) Electronics Packaging and Interconnects; (2) Optoelectronics and Optical Technologies; (3) Machine Architecture.