Physical Modeling of Low-K Dielectric Breakdown and the Estimation of Full Chip Lifetime

“该奖项是根据2009年美国复苏和再投资法案（公法111-5）资助的”最先进的芯片使用低k材料形成互连线之间的绝缘体。低k材料的使用降低了电容，这又降低了芯片中晶体管栅极之间的传播延迟。 为了减少延迟，每一代技术都涉及具有逐渐降低的k值的低k材料。 这些材料通过增加孔隙率形成，并且具有逐渐退化的可靠性特性。 理解用低k材料构建的芯片的可靠性是复杂的，因为可靠性是完整互连系统的函数，包括低k材料，帽层和阻挡层。 因此，不能孤立地研究材料，材料之间的界面在击穿中起着重要作用。 本研究通过开发击穿模拟模型及其对经验数据的校准，全面了解多孔低k介质的击穿。 后端介电击穿是复杂的，因为在多孔低k材料中的界面的作用和大量的缺陷和材料的不规则性。 这项工作研究了介电击穿在微观水平上，在多孔材料和界面（盖层和屏障），并建立模型的应力下通过材料和界面的传导。 模型的经验校准涉及新的方法，以消除内部和结构之间的线宽变化和测试结构尖端的场增强的影响。 该模型是用来建立一个工具来分析一个完整的芯片布局？的脆弱性后端介质击穿。 由此产生的工具应显着降低制造风险和设计响应。

"This award is funded under the American Recovery and Reinvestment Act of 2009 (Public Law 111-5)"State-of-the-art chips use low-k materials to form the insulator between interconnect lines. The use of low-k materials reduces capacitance, which in turn reduces the propagation delay between the transistor gates in a chip. To reduce delay, each technology generation involves low-k materials with progressively lower k values. These materials are formed by adding porosity and have progressively degraded reliability characteristics. Understanding the reliability of chips built with low-k materials is complicated, because reliability is a function of the complete interconnect system, including the low-k material, the cap layer, and the barrier. Hence, the materials cannot be studied in isolation, and the interfaces among the materials play a major role in breakdown. This research is developing a comprehensive understanding of breakdown of porous low-k dielectrics through the development of simulation models of breakdown and their calibration to empirical data. Backend dielectric breakdown is complicated because of the role of interfaces and the large number of defects and material irregularities in porous low-k materials. This work studies dielectric breakdown at the microscopic level, in porous materials and at interfaces (cap layer and barrier), and builds models of conduction through materials and at interfaces under stress. Empirical calibration of models involves new approaches to eliminate the impact of within and between structure linewidth variation and of field enhancement at test structure tips. The models are used to build a tool to analyze a full chip layout?s vulnerability to backend dielectric breakdown. The resulting tool should significantly reduce manufacturing risk and design respins.