SHF: Small: Collaborative Research: A Novel Method for the Performance Analysis of VLSI Circuits with Severe Parameter Value Variations due to Nano-scale Process

SHF：小型：协作研究：一种用于纳米级工艺导致参数值变化严重的 VLSI 电路性能分析的新方法

• 批准号: 1115556
• 负责人: Dian Zhou
• 金额: $ 17.5万
• 依托单位: University of Texas at Dallas
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-07-01 至 2015-06-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1115556&HistoricalAwards=false
• 关键词: SHF; Small; Collaborative; Research; Novel

The advance of VLSI technology has reached to 32nm feature size and below. For such a nano-scale process, lithography no longer produces the ideal shape/dimension of circuit components in a silicon wafer, and the corresponding electrical parameters may vary as large as 1/3 or more. A major concern in VLSI design is how to evaluate the circuits/systems performance made in such nano-scale process. In the other words, we want to know how much the performance specs will change due to variation in circuit parameters from their nominal values caused by the process uncertainties. The current research on performance robustness analysis is developed mainly along the line of the Monte-Carlo sampling method, or stochastic and statistical analysis methods. They all require a high level of computation complexity to achieve the required accuracy and one would like to avoid the evaluation of large number of samples to validate the performance range of a VLSI circuit/system. In this research the PIs propose a novel method for VLSI circuit performance robustness analysis which does not require evaluation of large numbers of samples. Instead, it computes only a few critical polynomials in frequency domain, or critical systems in time domain. It is a fundamentally new way to analyze VLSI circuit performance robustness. The consequent leap of computation efficiency would make nano-scale VLSI circuit design and its performance robustness analysis practically possible. The objectives of this project are: (i) to develop a solid theoretical basis for the performance robustness analysis of VLSI circuits in both frequency and time domains; (ii) to develop an efficient, novel method for computing VLSI circuit performance variation bounds and distribution (due to the process variation) without using the Monte-Carlo method.The broad impact of this project will be its potentially transformative effect on the robust analysis methods for VLSI circuits. This research will be integrated into the graduate education of the Ph.D. students at the two universities involved, and disseminated by publications in journals and presentations at conferences, a workshop and collaboration with industry, and will hopefully contribute to broad thinking across multiple disciplines.

VLSI技术的进步已经达到32nm及以下的特征尺寸。对于这样的纳米级工艺，光刻不再产生硅片中电路元件的理想形状/尺寸，相应的电气参数可能相差1/3甚至更多。VLSI设计中的一个主要问题是如何评估在这种纳米尺度工艺中制造的电路/系统性能。换句话说，我们想知道由于工艺不确定性引起的电路参数与标称值的变化，性能规格会发生多大的变化。目前对性能稳健性分析的研究主要是沿着蒙特卡罗抽样方法或随机和统计分析方法发展的。它们都需要高水平的计算复杂性来达到所需的精度，并且人们希望避免评估大量样本来验证VLSI电路/系统的性能范围。在这项研究中，pi提出了一种不需要评估大量样本的VLSI电路性能鲁棒性分析的新方法。相反，它只计算频域的几个关键多项式，或时域的关键系统。这是一种全新的分析VLSI电路性能鲁棒性的方法。计算效率的飞跃将使纳米级VLSI电路设计及其性能鲁棒性分析成为可能。该项目的目标是：(i)为VLSI电路在频率和时间域的性能鲁棒性分析提供坚实的理论基础；（ii）在不使用蒙特卡罗方法的情况下，开发一种高效、新颖的方法来计算VLSI电路性能变化界限和分布（由于工艺变化）。这个项目的广泛影响将是它对VLSI电路的鲁棒分析方法的潜在变革性影响。这项研究将整合到两所大学的博士研究生教育中，并通过期刊出版物、会议报告、研讨会和与工业界的合作来传播，并有望促进跨学科的广泛思考。