Research Initiation Award: Reducing the Impact of Synchronization Latency in Shared-Memory Multiprocessors

9410457 Adve本研究的目的是开发和评估减少共享内存多处理器中同步延迟影响的技术。最近的趋势表明，未来的微处理器将采用激进的技术（例如，多指令问题，动态调度）来利用指令级并行性。然而，当前的共享内存多处理器通常需要一个处理器在同步读取时暂停，直到读取完成，这阻碍了对未来单处理器的充分利用。本研究研究了两种减少同步延迟影响的方法：(a)显式同步的重叠延迟，(b)使用隐式同步（在可能的情况下）消除同步延迟。这项研究的主要内容包括：(1)一种基于保护指令的实用硬件技术，用于重叠获取操作；(2)通过使用显式和隐式同步的新组合来减轻隐式同步带来的实现开销；(3)以高级注释的形式确定信息，程序员可以提供这些信息来增强对指令级并行性的检测；(4)通过对实际应用的大量教学级模拟，对上述技术的有效性进行定量评估。这项研究是实现更广泛接受并行机器的必要步骤，因为它将通过更充分地利用下一代微处理器的潜力使机器更具成本效益，并将通过允许有效执行细粒度应用程序来扩大支持的应用类别。＊＊＊

9410457 Adve The objective of this research is to develop and evaluate techniques for reducing the impact of synchronization latency in shared-memory multiprocessors. Recent trends indicate that future microprocessors will employ aggressive techniques (e.g., multiple instruction issue, dynamic scheduling) to exploit instruction-level parallelism. Current shared-memory multiprocessors, however, usually require a processor to stall on synchronization reads until the read completes, precluding the full exploitation of future uniprocessors. The research studies two approaches for reducing the impact of synchronization latency: (a) overlapping latency of explicit synchronizations, and (b) using implicit synchronization (where possible) to eliminate synchronization latency. The key components of the study will be: (1) a practical hardware technique based on guarded instructions for overlapping acquire operations, (2) alleviating implementation overheads incurred with implicit synchronization by using a novel combination of explicit and implicit synchronization, (3) determining information in the form of high-level annotations that programmers can provide to enhance detection of instruction-level parallelism, and (4) a quantitative evaluation of the efficacy of the above techniques using extensive instruction-level simulations of real applications. This research is a necessary step towards enabling wider acceptance of parallel machines because it will enable machines to be more cost-effective by exploiting more fully the potential of next-generation microprocessors, and will broaden the supported class of applications by allowing the efficient execution of finer-grained applications. ***