SHF: Small: Hardware-Software Co-Designed Coherence: A Complete Coherence Solution for Performance-, Energy-, and Complexity-Efficiency

随着晶体管扩展带来的好处逐渐减少，计算系统未来的性能提升将越来越依赖于架构的进步。今天的处理器使用并行和越来越多的专业化来提供这种性能增长。高效的内存层次结构是实现这两种技术全部潜力的关键。一致性协议和内存一致性模型是内存层次结构的复杂性、性能和能量效率的核心。不幸的是，在各种系统中，一致性协议和一致性模型继续努力在复杂性，性能和能耗之间获得适当的平衡。最近，已经有关于混合硬件-软件协同设计协议的工作，例如DeNovo协议，其采用不同的方法，将纯硬件和纯软件协议的最佳组合。关键的见解是，如果软件是有纪律的，那么就有可能设计出更高效的硬件。DeNovo系统的多个版本相继放宽了软件限制。在课堂上向研究生和本科生介绍这种新技术将使他们更好地为未来的记忆趋势和挑战做好准备。通过出版物，研讨会，教程等传播这项研究的结果将为社区带来新的技术意识，并在学术界和工业界之间创造更多的协同作用。先前的工作已经确定了DeNovo作为一个通用系统的潜力，与最先进的系统相比具有显着的优势。然而，这项必要的工作仅限于简单的工作负载。要将DeNovo视为一个可行的系统，以供广泛的工业采用，需要展示一个可以运行复杂工作负载的集成系统（例如，操作系统）和遗留二进制文件。该项目解决了剩余的研究问题，以实现这一目标。虽然这项工作是由对混合硬件-软件一致性协议的考虑驱动的，但智力贡献也超出了这些协议;例如，集成支持高效，一致的数据访问，使用各种学科，从完全非结构化到高度结构化，静态可分析的访问;系统探索宽松的原子，在当前内存一致性模型中广泛接受的困难;并以一致性中立的方式理解并发数据结构和系统代码。

As the benefits from transistor scaling slow down, future performance increases in computing systems will increasingly rely on architectural advances. Today processors use parallelism and increasing amounts of specialization to provide this performance growth. An efficient memory hierarchy is key to achieving the full potential of both of these techniques. The coherence protocol and memory consistency model are at the heart of the complexity-, performance-, and energy-efficiency of the memory hierarchy. Unfortunately, across a variety of systems, coherence protocols and consistency models continue to struggle to obtain an appropriate balance between complexity, performance, and energy consumption. Recently, there has been work on hybrid hardware-software co-designed protocols, exemplified by the DeNovo protocol, which takes a different approach, combining the best of pure hardware and pure software protocols. The key insight is that if software is disciplined, then it is possible to design more efficient hardware. Multiple versions of the DeNovo system have successively relaxed the software restrictions. Introducing such a new technology in classrooms to both graduate and undergraduate students will better prepare them for future memory trend and challenges. Disseminating the results of this research via publications, seminars, tutorials etc. will bring new technology awareness to the community and create more synergy among academia and industry. Prior work has established the potential for DeNovo as a general-purpose system with significant advantages over the state-of-the-art. However, this work of necessity has been limited to simple workloads. Consideration of DeNovo as a viable system for widespread industrial adoption requires demonstrating an integrated system that can run complex workloads (e.g., operating systems) and legacy binaries. This project addresses the remaining research issues to achieve this goal. Although this work is driven by considerations for hybrid hardware-software coherence protocols, the intellectual contributions extend beyond those protocols as well; e.g., integrated support for efficient, coherent data accesses using a variety of disciplines ranging from completely unstructured to highly structured, statically analyzable accesses; a systematic exploration of relaxed atomics, a widely accepted difficulty in current memory consistency models; and understanding concurrent data structures and system code in a coherence neutral way.