Lifetime Reliability Aware Microprocessors

随着CMOS规模的不断扩大，越来越小的特征尺寸和越来越高的功率密度正在加速处理器中磨损或老化相关的硬故障的发生。当前较低级别的解决方案策略可能不足以解决这种生命周期可靠性问题。本研究提倡更高层次的微架构解决方案，以提高处理器的生命周期可靠性。这项工作的第一个组成部分是开发和验证微架构级模型、度量和包含关键故障机制及其扩展行为的工具。第二部分为寿命可靠性问题开发了新的体系结构解决方案，包括动态可靠性管理和选择性结构冗余。在过去的几十年里，CMOS技术的扩展带来的性能优势使信息革命成为可能，几乎影响了社会的各个方面。本提案中提出的寿命可靠性问题是CMOS扩展持续获益的关键障碍之一。提出的工作旨在开发一种全新的方法来解决这个问题，从而能够满足所有处理器制造商的关键可靠性目标。这项工作是与IBM的研究人员合作进行的，IBM将提供所需的工业专业知识以及技术转移的途径。

Lifetime Reliability Aware MicroprocessorsAs CMOS scaling continues, increasingly smaller feature sizes and increasing power densities are accelerating the onset of wear-out or aging-related hard failures in processors. Current lower-level solution strategies will likely be inadequate to address this lifetime reliability problem. This research advocates higher-level, microarchitectural solutions for processor lifetime reliability. The first component of this work is in the development and validation of microarchitecture-level models, metrics, and tools that incorporate key failure mechanisms and their scaling behavior. The second component develops novel architectural solutions for the lifetime reliability problem, including dynamic reliability management and selective structural redundancy. The performance benefits from CMOS technology scaling over the last several decades have enabled the information revolution that has affected virtually every aspect of society. The problem of lifetime reliability addressed in this proposal is one of the key impediments to seeing continued benefits from CMOS scaling. The proposed work seeks to develop a fundamentally new approach to address this problem that will enable meeting the reliability goals critical for all processor manufacturers. This work is in collaboration with researchers from IBM which will provide needed industrial expertise as well as a path for technology transfer.