Quality vs. Cost Tradeoffs in VLSI Testing: An Empirical Analysis of Sematech Test Data

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Two significant components of VLSI manufacturing test cost are the test length, and the reject rate. The latter is the rate at which bad devices escape detection by the test. This research explores a new approach to estimate the reject rate so that optimum balance can be struck between the test length and the reject rate. The approach includes extensions to handle multiple types of tests that are commonly employed by the manufacturers, e.g. stuck-at, IDDQ, delay, and functional. Analytical methods for estimating the reject rate are too complex to capture accurately all interactions among parameters, which leads to unreliable reject rate estimates. In this project an empirical, yet robust model is being developed. It is based on properties observed in tester data that are demonstrated to be invariant for a wide range of manufacturing technologies and types of tests.