Design for Testability and Test Generation with Multiple Clocks

本研究是针对时钟同步电路的测试性设计（DFT），以及相关的测试生成算法。研究方法是将触发器分为两组，每组在测试模式下由自己独立的时钟线控制。结果是将原始状态机分解为两个通信子机，并将触发器分组，从而简化测试生成过程。触发器分区是用触发器连通性的图表示来表示的。实现了一种双时钟分解算法。在测试生成中，现有的测试生成器被改编为DFT方案的早期证明。此外，基于标准时间框架扩展的二维泛化的测试生成算法正在实现并针对基准电路进行测试。

This research is on design for testability (DFT), and associated test generation algorithms for clocked synchronous circuits. The research approach is to partition the flip-flops into tow groups, each controllable by its own independent clock line in the test mode. The result is the decomposition of the original state machine into two communicating submachines, with flip-flops grouped so as to simplify the test generation process. Flip-flop partitioning is stated in terms of a graph representation of flip- flop connectivity. A two clock decomposition algorithm is being implemented. In test generation, existing test generators are being adapted to serve as an early proof of the DFT scheme. Also, a test generation algorithm, based on a two dimensional generalization of the standard time frame expansion is being implemented and tested against benchmark circuits.