Design for Testability and Test Generation with Multiple Clocks

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This research is on design for testability (DFT), and associated test generation algorithms for clocked synchronous circuits. The research approach is to partition the flip-flops into tow groups, each controllable by its own independent clock line in the test mode. The result is the decomposition of the original state machine into two communicating submachines, with flip-flops grouped so as to simplify the test generation process. Flip-flop partitioning is stated in terms of a graph representation of flip- flop connectivity. A two clock decomposition algorithm is being implemented. In test generation, existing test generators are being adapted to serve as an early proof of the DFT scheme. Also, a test generation algorithm, based on a two dimensional generalization of the standard time frame expansion is being implemented and tested against benchmark circuits.