Design for Testability and Test Generation with Multiple Clocks

使用多个时钟进行可测试性和测试生成的设计

• 批准号: 9015115
• 负责人: Sharad Seth
• 金额: $ 6.8万
• 依托单位: University of Nebraska-Lincoln
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1991
• 资助国家: 美国
• 起止时间: 1991-03-15 至 1993-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9015115&HistoricalAwards=false
• 关键词: Design; Testability; Test; Generation; Multiple

This research is on design for testability (DFT), and associated test generation algorithms for clocked synchronous circuits. The research approach is to partition the flip-flops into tow groups, each controllable by its own independent clock line in the test mode. The result is the decomposition of the original state machine into two communicating submachines, with flip-flops grouped so as to simplify the test generation process. Flip-flop partitioning is stated in terms of a graph representation of flip- flop connectivity. A two clock decomposition algorithm is being implemented. In test generation, existing test generators are being adapted to serve as an early proof of the DFT scheme. Also, a test generation algorithm, based on a two dimensional generalization of the standard time frame expansion is being implemented and tested against benchmark circuits.

本研究是关于可测试性设计（DFT），以及相关的 时钟同步电路的测试生成算法。 的 研究方法是将触发器分成两组， 在测试中每个都可由其自己的独立时钟线控制 模式 其结果是原始状态的分解 一台机器分成两个通信的子机器，触发器分组 从而简化测试生成过程。 触发器 分区是根据翻转的图形表示来陈述的， 触发器连接 两个时钟分解算法正在被 切实贯彻 在测试生成中，现有的测试生成器 适合用作DFT方案的早期证明。 还有， 一种测试生成算法，基于二维 标准时间范围扩展的一般化正在 实现并针对基准电路进行测试。