A Unified Approach to Testing and Verification of Designs Synthesized from High-Level Specifications

本研究为设计验证与制造测试相关的测试问题发展出一个统一的架构。设计验证问题转化为扩展有限状态机（EFSM）中的可达性问题，设计验证测试对应于EFSM表示中的输入输出序列跟踪路径。它们是通过解决涉及数据寄存器、内部总线和主输入的线性和非线性约束而得到的。基于线性约束的封闭形式解可以在多项式时间内求出的结果，我们探索了几种约束求解的搜索策略。制造测试是通过完全扩展部分指定的验证向量，以达到最大覆盖率的门级电路描述中的故障。验证和测试序列可以通过反馈迭代地改进。本研究的贡献包括复杂电路的建模工具、约束求解问题的算法和新的故障覆盖度量。

This research develops a unified framework for the test problems related todesign verification and manufacturing tests. The design verificationproblem translates to the reachability problem in an extended finite statemachine (EFSM) derived from the register-transfer-level specification.Design-verification tests correspond to input-output sequences tracingpaths in the EFSM representation. They are derived by solving linear andnonlinear constraints involving data registers, internal buses, and primaryinputs. Several search strategies for constraint solving are being exploredbased on our result that closed form solutions to linear constraints can becomputed in polynomial time. Manufacturing tests are obtained by fullyexpanding partially specified verification vectors so as to achieve maximumcoverage of faults in the gate-level circuit description. The verificationand test sequences can be iteratively refined through feedback. Thecontributions of this research include modeling tools for complex circuits,algorithms for constraint- solving problem, and new measures of faultcoverage.