NSF CNPq Collaborative Research on Design Environments for Application-Specific Programmable Processors

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This research is on embedded systems design tools for building customapplication-specific instruction processor (ASIP) architectures that are nobigger, or no more complex than necessary. Developing an ASIP, not onlyrequires hardware design, but also requires the use of a set of evaluationtools such as an assembler, compiler and simulator. This investigation usesa processor description to serve as a common starting point for thedevelopment of these tools, as well as for hardware synthesis. The ISDLlanguage, being developed at MIT, for exactly this purpose is being used indeveloping a complete software development environment, as well as hardwaregeneration. The simulator is used to obtain clock cycle estimates onapplication code, and to evaluate the overall architecture performance.Synthesis of processor datapaths enables hardware generation and providesaccurate, cycle-time estimates. To support software compilation, aretargetable assembler, code generator and optimizer will be developed thatreceive as input both a machine description in ISDL, and the program to becompiled onto the described machine. New optimizations to produce code ofthe highest quality in a reasonable amount of time are being evaluated. Thebase of our retargetable compiler is SPAM, an embedded compiler frameworkthat has been developed by researchers at MIT, Princeton and UNICAMP,Brazil. In many cases, application code is not written in high-levelprogramming languages, and it is necessary to deal with assembly or legacycode. Thus automatic methods for optimized binary-to-binary translation arebeing investigated. To do this, the legacy binary/assembly code isdecompiled to intermediate forms used by our compiler infrastructure andthen using the optimizing compiler technology to generate high-qualityassembly for the target architecture.