SHF: Medium: Collaborative Research: Throughput-Driven Multi-Core Architecture and a Compilation System

SHF：中：协作研究：吞吐量驱动的多核架构和编译系统

• 批准号: 0904598
• 负责人: Srini Devadas
• 金额: $ 45万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2009
• 资助国家: 美国
• 起止时间: 2009-09-01 至 2012-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0904598&HistoricalAwards=false
• 关键词: SHF; Medium; Collaborative; Research; Throughput

Computing substrates such as multi-core processors or Field Programmable Gate Arrays (FPGAs) share the characteristic of having two-dimensional arrays of processing elements interconnected by a routing fabric. At one end of the spectrum, FPGAs have single-output programmable logic functions, and at the other end, multi-core chips have complex 32/64-bit processing cores. For different applications, different programmable substrates produce the best area-power-performance tradeoffs. This project is developing a large-scale multi-core substrate that has hundreds or thousands of simple processing cores along with a compilation system that maps computations onto this fabric. This many-core architecture, named Diastolic Array, is coarser-grained than FPGAs but finer-grained than conventional multi-cores. To efficiently exploit such a large number of processing cores, the architecture needs spatially mapping a computation to processing cores and communication to the point-to-point interconnect network. To be practically viable, this mapping process must be automated and effective. The project addresses this challenge by simultaneously developing hardware architecture and a compilation system.A diastolic array chip is expected to outperform FPGAs or general-purpose processors on an interesting class of applications, enabling more efficient prototyping and low-volume production. The outcomes of this project such as statically-configured interconnection architecture with associated algorithms for routing and resource allocation will also be applicable to other multi-core designs. Finally, the project is developing a new parallel processing module for an undergraduate computer architecture class to give sophomores early exposure to parallel hardware, experience with writing parallel programs and using compilers that exploit parallelism.

诸如多核处理器或现场可编程门阵列(FGA)的计算基板共享具有由布线结构互连的处理元件的二维阵列的特征。在频谱的一端，现场可编程门阵列具有单输出可编程逻辑功能，而在另一端，多核芯片具有复杂的32/位处理核心。对于不同的应用，不同的可编程基板产生最佳的面积-功率-性能折衷。该项目正在开发一种大规模多核基板，它具有数百或数千个简单的处理核心，以及一个将计算映射到该结构上的编译系统。这种名为舒张期阵列的多核架构比现场可编程门阵列的粒度更粗，但比传统的多核更细粒度。为了有效地利用如此大量的处理核，该体系结构需要在空间上将计算映射到处理核，并将通信映射到点对点互连网络。为了实际可行，这一测绘过程必须是自动化和有效的。该项目通过同时开发硬件架构和编译系统来应对这一挑战。预计舒张期阵列芯片在一类有趣的应用程序上的表现将超过现场可编程门阵列或通用处理器，从而实现更高效的原型制作和小批量生产。该项目的成果，例如静态引导的互连体系结构以及相关的布线和资源分配算法，也将适用于其他多核设计。最后，该项目正在为一门本科计算机体系结构课程开发一个新的并行处理模块，让大二学生及早接触并行硬件，体验编写并行程序和使用利用并行性的编译器的经验。