SHF: Medium: Collaborative Research: Throughput-Driven Multi-Core Architecture and a Compilation System

SHF:中:协作研究:吞吐量驱动的多核架构和编译系统

基本信息

  • 批准号:
    0904598
  • 负责人:
  • 金额:
    $ 45万
  • 依托单位:
  • 依托单位国家:
    美国
  • 项目类别:
    Standard Grant
  • 财政年份:
    2009
  • 资助国家:
    美国
  • 起止时间:
    2009-09-01 至 2012-08-31
  • 项目状态:
    已结题

项目摘要

Computing substrates such as multi-core processors or Field Programmable Gate Arrays (FPGAs) share the characteristic of having two-dimensional arrays of processing elements interconnected by a routing fabric. At one end of the spectrum, FPGAs have single-output programmable logic functions, and at the other end, multi-core chips have complex 32/64-bit processing cores. For different applications, different programmable substrates produce the best area-power-performance tradeoffs. This project is developing a large-scale multi-core substrate that has hundreds or thousands of simple processing cores along with a compilation system that maps computations onto this fabric. This many-core architecture, named Diastolic Array, is coarser-grained than FPGAs but finer-grained than conventional multi-cores. To efficiently exploit such a large number of processing cores, the architecture needs spatially mapping a computation to processing cores and communication to the point-to-point interconnect network. To be practically viable, this mapping process must be automated and effective. The project addresses this challenge by simultaneously developing hardware architecture and a compilation system.A diastolic array chip is expected to outperform FPGAs or general-purpose processors on an interesting class of applications, enabling more efficient prototyping and low-volume production. The outcomes of this project such as statically-configured interconnection architecture with associated algorithms for routing and resource allocation will also be applicable to other multi-core designs. Finally, the project is developing a new parallel processing module for an undergraduate computer architecture class to give sophomores early exposure to parallel hardware, experience with writing parallel programs and using compilers that exploit parallelism.
诸如多核处理器或现场可编程门阵列(FPGA)的计算基板共享具有通过路由结构互连的处理元件的二维阵列的特性。一方面,FPGA具有单输出可编程逻辑功能,另一方面,多核芯片具有复杂的32/64位处理核心。对于不同的应用,不同的可编程衬底产生最佳的面积-功率-性能权衡。这个项目正在开发一个大规模的多核基板,它有数百或数千个简单的处理核心沿着编译系统,将计算映射到这个结构上。这种多核架构名为Diastolic Array,比FPGA粒度更粗,但比传统的多核粒度更细。为了有效地利用这样大量的处理核,架构需要在空间上将计算映射到处理核并且将通信映射到点对点互连网络。为了切实可行,这一映射过程必须自动化和有效。该项目通过同时开发硬件架构和编译系统来应对这一挑战。舒张阵列芯片有望在一类有趣的应用中超越FPGA或通用处理器,从而实现更高效的原型设计和小批量生产。该项目的成果,如静态控制fi具有用于路由和资源分配的关联算法的互连架构也将适用于其他多核设计。最后,该项目正在开发一个新的并行处理模块,为本科计算机体系结构类,让初学者早期接触并行硬件,编写并行程序的经验,并使用编译器,利用并行。

项目成果

期刊论文数量(0)
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会议论文数量(0)
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Srini Devadas其他文献

Self-aware computing in the Angstrom processor
Angstrom 处理器中的自我感知计算
  • DOI:
  • 发表时间:
    2012
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Henry Hoffmann;Jim Holt;George Kurian;Eric Lau;Martina Maggio;Jason E. Miller;Sabrina M. Neuman;Mahmut E. Sinangil;Yildiz Sinangil;A. Agarwal;A. Chandrakasan;Srini Devadas
  • 通讯作者:
    Srini Devadas
Hardware Mechanisms for Memory Authentication
内存验证的硬件机制
  • DOI:
  • 发表时间:
    2003
  • 期刊:
  • 影响因子:
    0
  • 作者:
    Edward Suh;Dwaine E. Clarke;B. Gassend;Marten Van Dijk;Srini Devadas;G. Suh;Srini Devadas
  • 通讯作者:
    Srini Devadas

Srini Devadas的其他文献

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{{ truncateString('Srini Devadas', 18)}}的其他基金

SaTC: CORE: Medium: Provably Secure, Usable, and Performant Enclaves in Multicore Processors
SaTC:CORE:中:多核处理器中可证明安全、可用且高性能的 Enclave
  • 批准号:
    2115587
  • 财政年份:
    2021
  • 资助金额:
    $ 45万
  • 项目类别:
    Continuing Grant
SaTC: CORE: Medium: Collaborative: Hardening Off-the-Shelf Software Against Side Channel Attacks
SaTC:核心:媒介:协作:强化现成软件以抵御侧通道攻击
  • 批准号:
    1955270
  • 财政年份:
    2020
  • 资助金额:
    $ 45万
  • 项目类别:
    Continuing Grant
SaTC: CORE: Small: Design of Efficient, Horizontally-Scaling, and Strongly Anonymous Communication Networks
SaTC:核心:小型:高效、水平扩展和强匿名通信网络的设计
  • 批准号:
    1813087
  • 财政年份:
    2018
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
SPX: Collaborative Research: Distributed Database Management with Logical Leases and Hardware Transactional Memory
SPX:协作研究:具有逻辑租赁和硬件事务内存的分布式数据库管理
  • 批准号:
    1822920
  • 财政年份:
    2018
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
STARSS: Small: Trapdoor Computational Fuzzy Extractors
STARSS:小型:活板门计算模糊提取器
  • 批准号:
    1523572
  • 财政年份:
    2015
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
TWC: TTP Option: Frontier: Collaborative: MACS: A Modular Approach to Cloud Security
TWC:TTP 选项:前沿:协作:MACS:云安全的模块化方法
  • 批准号:
    1413920
  • 财政年份:
    2014
  • 资助金额:
    $ 45万
  • 项目类别:
    Continuing Grant
XPS: FULL: DSD: Collaborative Research: Moving the Abyss: Database Management on Future 1000-core Processors
XPS:完整:DSD:协作研究:移动深渊:未来 1000 核处理器上的数据库管理
  • 批准号:
    1438967
  • 财政年份:
    2014
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
TWC: Small: Ascend: Architecture for Secure Computation on Encrypted Data
TWC:小型:Ascend:加密数据安全计算架构
  • 批准号:
    1317763
  • 财政年份:
    2013
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
EAGER: Collaborative: Holistic Security for Cloud Computing: Oblivious Computation
EAGER:协作:云计算的整体安全性:不经意的计算
  • 批准号:
    1347279
  • 财政年份:
    2013
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant
SHF: Small: Directoryless Shared Memory Using Execution Migration
SHF:小型:使用执行迁移的无目录共享内存
  • 批准号:
    1116372
  • 财政年份:
    2011
  • 资助金额:
    $ 45万
  • 项目类别:
    Standard Grant

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