SHF: Small: Directoryless Shared Memory Using Execution Migration

SHF：小型：使用执行迁移的无目录共享内存

• 批准号: 1116372
• 负责人: Srini Devadas
• 金额: $ 40万
• 依托单位: Massachusetts Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2011
• 资助国家: 美国
• 起止时间: 2011-09-01 至 2015-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1116372&HistoricalAwards=false
• 关键词: SHF; Small; Directoryless; Shared; Memory

The increase in processor clock frequencies from 1980-2003 has slowed down significantly in recent years. To improve computer performance computer architects are exploring parallel architectures including many-core architectures. In a many-core or multi-core architecture, processor cores with relatively low complexity are connected to memory and to each other via high-bandwidth on-chip interconnect. The most popular programming model for multi-cores is that of shared memory. In this memory model, programmers write different threads that can run on different processors all of which can share a single memory space. This means that the on-chip cache memory on the multi-core chip should behave like a large shared cache. Unfortunately, current schemes for cache coherence either suffer from lack of scalability or require large directories at each core significantly increasing chip area and power. A directoryless cache coherence scheme is being investigated in this project that relies on the mechanism of execution migration. In execution migration, a thread?s context or state moves to the processor in whose cache the data resides. An important advantage of an execution migration architecture is that only a one-way trip is required to access data, since the thread moves to access data. In conventional data migration architectures, a round-trip is required to access data ? a request is sent to the location where the data resides and then the data is sent to the requesting thread. Further, only one copy of data need be present on chip if execution migration is used, since threads can move. This means that cache coherence is trivially ensured. Moreover, the chip can store more distinct data, since data is not replicated and this reduces off-chip access rates. Finally, an execution migration architecture can exploit the plentiful on-chip bandwidth available to speed up thread migration, thereby reducing data access latency.There are challenges associated with this architecture corresponding to contention for shared data across multiple threads, and the energy required to move thread contexts. The first challenge is being met through judicious replication of data at the program source level or compiler level. In particular, limited read copies of data are created across multiple threads. Since these copies only exist in between two writes to the data, coherence is ensured as before without need for complex coherence logic. However, contention for shared data is significantly reduced. The second challenge of energy consumption is being met through migration of partial thread contexts ? if a stack machine is used as the processor core, energy consumption can be reduced by migrating a subset of the thread context corresponding to the top part of the stack instead of the entire stack.In this project, an Execution Migration Machine with over 100 cores is being designed, and being evaluated using cycle-accurate simulation, and critical elements of the machine are being built on a Field Programmable Gate Array (FPGA). This project has the potential to meet the scalability and programmability challenges that face shared memory multi-core architectures. The Execution Migration Machine design will shed insight into how best thread migration can be used to enhance multi-core performance, possibly in combination with data migration. If successful, the project will impact the design of future multi-core processors through intelligent use of program and data migration.

1980-2003年间处理器时钟频率的增长在最近几年已显著放缓。为了提高计算机性能，计算机架构师正在探索并行体系结构，包括多核体系结构。在多核或多核体系结构中，具有相对较低复杂性的处理器核通过高带宽片上互连连接到存储器并相互连接。最流行的多核编程模型是共享内存模型。在这种内存模型中，程序员编写不同的线程，这些线程可以在不同的处理器上运行，所有这些处理器都可以共享一个内存空间。这意味着多核芯片上的片上高速缓存应该像大型共享高速缓存一样运行。遗憾的是，当前用于高速缓存一致性的方案要么缺乏可伸缩性，要么需要在每个核心处使用大目录，从而显著增加了芯片面积和功率。本项目正在研究一种依赖于执行迁移机制的无目录高速缓存一致性方案。在执行迁移中，线程--S上下文或状态--移动到数据驻留在其缓存中的处理器。执行迁移体系结构的一个重要优势是只需要单向访问数据，因为线程会移动来访问数据。在传统的数据迁移体系结构中，需要往返访问数据？请求被发送到数据驻留的位置，然后数据被发送到请求线程。此外，如果使用执行迁移，则只需要在芯片上存在数据的一个副本，因为线程可以移动。这意味着高速缓存一致性得到了微不足道的保证。此外，芯片可以存储更多不同的数据，因为数据不被复制，这降低了芯片外的访问率。最后，执行迁移体系结构可以利用丰富的片上带宽来加速线程迁移，从而减少数据访问延迟。与该体系结构相关联的挑战对应于跨多个线程的共享数据的争用以及移动线程上下文所需的能量。第一个挑战是通过在程序源代码级别或编译器级别明智地复制数据来应对。特别是，跨多个线程创建有限的数据读取副本。由于这些副本仅存在于对数据的两次写入之间，因此可以像以前一样确保一致性，而不需要复杂的一致性逻辑。然而，对共享数据的争用显著减少。能源消耗的第二个挑战是通过迁移部分线程上下文来解决吗？在本项目中，正在设计一台拥有100多个核心的执行迁移机，并使用精确的周期模拟对其进行评估，并且将机器的关键部件构建在现场可编程门阵列(FPGA)上。该项目具有满足共享内存多核架构所面临的可扩展性和可编程性挑战的潜力。执行迁移机器的设计将深入了解如何使用最好的线程迁移来增强多核性能，并可能与数据迁移结合使用。如果成功，该项目将通过智能使用程序和数据迁移来影响未来多核处理器的设计。