Reliability Study of Oxidized Deposited Polysilicon (ODP) Gate Oxide for Silicon Carbide Power Transistors

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9906543AyersSilicon carbide (SiC) is a wide-bandgap semiconductor of great interest for high-power and high-temperature applications. In particular, SiC metal oxide semiconductor field effect transistors (MOSFET's) are promising for high-power, high-temperature applications because of the inherent temperature stability of MOSFET's and because of the high quality of the oxide, which is SiO2. Of the various MOSFET designs, the U-groove MOSFET (U-MOSFET) is particularly well suited for high-power applications due to its high current capability. U-MOSFET's may be fabricated in SiC using epitaxy and ion implantation, followed by anisotropic etching to form the U-groove, and then thermal oxidation to form the gate oxide. This approach, although standard in Si technology, is problematic in SiC because of the strong anisotropy of the thermal oxidation. It has been shown recently that this problem can be solved by the deposition of polycrystalline silicon, followed by thermal oxidation. This two-step process results in gate-quality oxide with uniform thickness over U-groove structures. In addition, the use of oxidized deposited polysilicon (ODP) gate oxide provides great flexibility in nitridation of the gate oxide. Initial studies indicate that nitridation of the gate oxide in SiC MOSFET's can reduce hot carrier injection and improve reliability. To date however, there have been few studies of the reliability of gate oxides in SiC MOSFET's under high-temperature, high-field conditions, and there have been no such studies in the case of ODP gate oxide. The PI's propose to study the reliability of ODP gate oxide on SiC under high-stress conditions.For this study, polysilicon will be deposited in a chemical vapor deposition system on {0001} 4H SiC wafers. Polysilicon deposition will be carried out using silane diluted in UHP hydrogen, at 700oC. The polysilicon, approximately 100 nm thick, will be oxidized in dry O2 at 1100oC for a time sufficient to consume all of the polysilicon. Metal gates will then be deposited by the evaporation of aluminum or the deposition of doped polysilicon. The PI's will study the reliability of the resulting MOS capacitors under high-stress conditions. The MOS capacitors will be held at high field (106-107 V/cm) and high temperature (100-300oC). The PI's will periodicallycheck the flat band voltage throughout the course of the stressing to assess the degradation. The PI's will also use photo-CV measurements to determine the oxide interface state density before and after stressing.***