Patterned Heteroepitaxial Processing: A New Approach to Mismatched Heteroepitaxy for the Fabrication of High-Performance Semiconductor Devices

图案化异质外延加工：一种用于制造高性能半导体器件的失配异质外延的新方法

• 批准号: 9905874
• 负责人: John Ayers
• 金额: $ 3.53万
• 依托单位: University of Connecticut
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 1999
• 资助国家: 美国
• 起止时间: 1999-07-01 至 2000-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=9905874&HistoricalAwards=false
• 关键词: Patterned; Heteroepitaxial; Processing; New; Approach

9905874AyersMismatched heteroepitaxy of semiconductors is of considerable interest for the fabrication of many novel devices and integrated circuits. This is because relatively few semiconductor substrates are available with high crystal perfection and suitable electronic properties. On the other hand, many semiconductors not lattice-matched to the common substrate wafers (Si, GaAs, and InP) have important potential applications for high-speed digital electronics, microwave integrated circuits, optoelectronics, optoelectronic integrated circuits, and solar cells. Unfortunately, the use of highly-mismatched heteroepitaxial semiconductors in devices and circuits has been quite limited due to the high densities of crystal defects such as threading dislocations (TD's) and stacking faults (SF's). These defects degrade the performance of both majority- and minority-carrier devices, resulting in high leakage currents and subthreshold degradation in field-effect transistors, poor current gain for bipolar transistors, poor efficiency and brightness in light emitting diodes, and rapid degradation and failure in injection lasers.At the present time, compliant substrates show great promise for reducing the defect densities in mismatched heteroepitaxial semiconductors. However, the compliant substrate method may be difficult to implement in the case of highly-mismatched semiconductors on large area substrates. This is because such applications require compliant layers only a few angstroms thick, which are difficult to produce by presently available techniques on large wafers. The PI's have proposed a new approach to the achievement of highly mismatched heteroepitaxial semiconductors free from threading dislocations, which is complementary to the compliant substrate approach. The PI's call their approach "patterned heteroepitaxial processing (PHP)."The PHP approach involves either patterned heteroepitaxy, or the patterning of continuous layers followed by post-growth annealing. Either variation of PBP should allow the achievement of material absolutely free from threading dislocations as long as the lateral size of the patterned regions is small enough. To date we have developed a quantitative model for the PHP method, but very few experiments have been done. Here they propose to perform an experimental evaluation of PHP. Although the technique applies quite generally to zinc blende semiconductors, they will focus on ZnSSe material deposited on GaAs substrates for this work. If this phase is successful, then further experimental verification will be warranted, especially with other heteroepitaxial material systems.The scope of the proposed work is the following. They will deposit continuous layers of ZnSSe on GaAs (001) substrates using metalorganic vapor phase epitaxy (MOVPE). Different compositions will allow them to tailor the lattice mismatch from +0.27% to -4%. They will pattern the ZnSSe layers after growth, to square and rectangular areas of different dimensions. After post-growth annealing the patterned areas will be characterized using wet chemical etching and scanning electron microscopy to evaluate their threading dislocation densities. They will use their existing quantitative model as a guide in designing our experiments. The results of the experiments will be used to develop their recommendations for the next phase of research.***

失配半导体异质外延在许多新型器件和集成电路的制造中引起了极大的兴趣。这是因为具有高晶体完备性和合适的电子性能的半导体衬底相对较少。另一方面，许多与普通衬底晶格不匹配的半导体(Si、GaAs和InP)在高速数字电子、微波集成电路、光电子学、光电集成电路和太阳能电池等领域具有重要的潜在应用。不幸的是，高度失配的异质外延半导体在器件和电路中的应用受到了相当大的限制，这是因为晶体缺陷的密度很高，如穿线位错(TD‘s)和层错(SF’s)。这些缺陷降低了多数载流子和少数载流子器件的性能，导致场效应晶体管的高泄漏电流和亚阈值退化，双极晶体管的电流增益较差，发光二极管的效率和亮度较低，以及注入激光器的快速退化和失效。目前，顺应性衬底在降低失配异质外延半导体中的缺陷密度方面显示出巨大的潜力。然而，在大面积衬底上高度失配的半导体的情况下，顺应衬底方法可能很难实现。这是因为这样的应用需要只有几埃厚的顺应层，这很难用目前可用的技术在大晶片上生产。PI已经提出了一种新的方法来获得高度失配的无线位错的异质外延半导体，这是对顺应性衬底方法的补充。PI‘s称他们的方法为“图案化异质外延处理(PHP)”。PHP方法包括图案化异质外延，或连续层的图案化和生长后的退火热处理。只要图案区的横向尺寸足够小，PBP的任何一种变化都应该允许获得完全没有丝状位错的材料。到目前为止，我们已经为PHP方法开发了一个定量模型，但做的实验很少。在这里，他们建议对PHP进行一次实验性评估。虽然这项技术适用于闪锌矿半导体，但在这项工作中，他们将重点放在沉积在砷化镓衬底上的锌SSe材料上。如果这一阶段成功，那么将有必要进行进一步的实验验证，特别是对其他异质外延材料系统。他们将使用金属有机气相外延(MOVPE)在GaAs(001)衬底上连续沉积多层ZnSSe。不同的成分将允许它们将晶格失配从+0.27%调整到-4%。它们将在生长后将ZnSSe层图案化为不同尺寸的正方形和长方形区域。在生长后退火后，将使用湿化学刻蚀和扫描电子显微镜对图案区进行表征，以评估它们的线位错密度。他们将使用他们现有的定量模型作为设计我们实验的指导。实验结果将用于为下一阶段的研究制定建议。*