Patterned Heteroepitaxial Processing: A New Approach to Mismatched Heteroepitaxy for the Fabrication of High-Performance Semiconductor Devices

点击翻译按钮获取中文摘要

9905874AyersMismatched heteroepitaxy of semiconductors is of considerable interest for the fabrication of many novel devices and integrated circuits. This is because relatively few semiconductor substrates are available with high crystal perfection and suitable electronic properties. On the other hand, many semiconductors not lattice-matched to the common substrate wafers (Si, GaAs, and InP) have important potential applications for high-speed digital electronics, microwave integrated circuits, optoelectronics, optoelectronic integrated circuits, and solar cells. Unfortunately, the use of highly-mismatched heteroepitaxial semiconductors in devices and circuits has been quite limited due to the high densities of crystal defects such as threading dislocations (TD's) and stacking faults (SF's). These defects degrade the performance of both majority- and minority-carrier devices, resulting in high leakage currents and subthreshold degradation in field-effect transistors, poor current gain for bipolar transistors, poor efficiency and brightness in light emitting diodes, and rapid degradation and failure in injection lasers.At the present time, compliant substrates show great promise for reducing the defect densities in mismatched heteroepitaxial semiconductors. However, the compliant substrate method may be difficult to implement in the case of highly-mismatched semiconductors on large area substrates. This is because such applications require compliant layers only a few angstroms thick, which are difficult to produce by presently available techniques on large wafers. The PI's have proposed a new approach to the achievement of highly mismatched heteroepitaxial semiconductors free from threading dislocations, which is complementary to the compliant substrate approach. The PI's call their approach "patterned heteroepitaxial processing (PHP)."The PHP approach involves either patterned heteroepitaxy, or the patterning of continuous layers followed by post-growth annealing. Either variation of PBP should allow the achievement of material absolutely free from threading dislocations as long as the lateral size of the patterned regions is small enough. To date we have developed a quantitative model for the PHP method, but very few experiments have been done. Here they propose to perform an experimental evaluation of PHP. Although the technique applies quite generally to zinc blende semiconductors, they will focus on ZnSSe material deposited on GaAs substrates for this work. If this phase is successful, then further experimental verification will be warranted, especially with other heteroepitaxial material systems.The scope of the proposed work is the following. They will deposit continuous layers of ZnSSe on GaAs (001) substrates using metalorganic vapor phase epitaxy (MOVPE). Different compositions will allow them to tailor the lattice mismatch from +0.27% to -4%. They will pattern the ZnSSe layers after growth, to square and rectangular areas of different dimensions. After post-growth annealing the patterned areas will be characterized using wet chemical etching and scanning electron microscopy to evaluate their threading dislocation densities. They will use their existing quantitative model as a guide in designing our experiments. The results of the experiments will be used to develop their recommendations for the next phase of research.***