Multithreading: A Viable Approach for High Performance Single Chip Architecture

多线程：高性能单芯片架构的可行方法

• 批准号: 0073527
• 负责人: Jean-Luc Gaudiot
• 金额: $ 42.17万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2000
• 资助国家: 美国
• 起止时间: 2000-08-15 至 2002-02-28
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0073527&HistoricalAwards=false
• 关键词: Multithreading; Viable; Approach; Performance; Single

Most modern single processor architectures focus on exploiting instruction-level parallelism. However, despite continued performance improvements, there is increasing doubt that aggressive ILP architecture techniques would continue bringing the desired improvements and that there will come about a diminishing return in the performance of single-chip architectures.Multithreaded execution models promise to exploit thread-level parallelism (TLP) beyond a pure ILP approach. Multithreading can be applied directly at the level of uniprocessor instruction-set architectures. For example, Simultaneous MultiThreading (SMT) is a promising approach, which is attracting the attention of a number of academic and industrial research groups. This technique allows the various pipelines of a "superscalar" processor to be efficiently utilized by scheduling from several "coarse-grain" threads of one (or several) program(s). Although exploiting both ILP and TLP is attractive, the following questions are investigated in the project:- Can an architecture model, which integrates fine-grain multithreading support with a coarse-grain multithreaded architecture model such as SMT, be developed?- What are the design trade-off when mapping these architecture features to single-chip implementations?- What compiling methodology for the proposed architecture model would exploit thread-level parallelism at both coarse and fine-grain levels?

大多数现代单处理器体系结构专注于开发并行级并行。然而，尽管不断的性能改进，有越来越多的怀疑，积极的ILP架构技术将继续带来所需的改进，并会有关于单芯片architecture. Multi线程执行模型的性能回报递减承诺利用线程级并行（TLP）超越了纯ILP的方法。多线程可以直接应用于单处理器部署集架构级别。例如，同时多线程（SMT）是一种很有前途的方法，它吸引了许多学术和工业研究小组的注意。该技术允许通过从一个（或多个）程序的多个“粗粒度”线程进行调度来有效地利用“超标量”处理器的各种流水线。虽然同时利用ILP和TLP很有吸引力，但在该项目中研究了以下问题：-可以开发一个架构模型，将细粒度多线程支持与粗粒度多线程架构模型（如SMT）集成在一起吗？-在将这些架构特性映射到单芯片实现时，设计权衡是什么？对于建议的架构模型，什么编译方法可以在粗粒度和细粒度级别上利用线程级并行性？