Multithreading: A Viable Approach for High Performance Single Chip Architecture

大多数现代单处理器体系结构都侧重于利用指令级并行性。然而，尽管性能不断提高，但越来越多的人怀疑，激进的ILP体系结构技术将继续带来期望的改进，并且单芯片体系结构的性能回报将会减少。多线程执行模型承诺在纯ILP方法之外利用线程级并行性（TLP）。多线程可以直接应用于单处理器指令集架构的级别。例如，同步多线程（SMT）是一种很有前途的方法，它吸引了许多学术和工业研究小组的注意。这种技术允许通过调度一个（或多个）程序的几个“粗粒度”线程来有效地利用“超标量”处理器的各种管道。虽然同时开发ILP和TLP很有吸引力，但在项目中研究了以下问题：—是否可以开发一个架构模型，将细粒度多线程支持与粗粒度多线程架构模型（如SMT）集成在一起？-在将这些架构特征映射到单芯片实现时，设计权衡是什么？-建议的架构模型的编译方法将在粗粒度和细粒度级别上利用线程级别的并行性？

Most modern single processor architectures focus on exploiting instruction-level parallelism. However, despite continued performance improvements, there is increasing doubt that aggressive ILP architecture techniques would continue bringing the desired improvements and that there will come about a diminishing return in the performance of single-chip architectures.Multithreaded execution models promise to exploit thread-level parallelism (TLP) beyond a pure ILP approach. Multithreading can be applied directly at the level of uniprocessor instruction-set architectures. For example, Simultaneous MultiThreading (SMT) is a promising approach, which is attracting the attention of a number of academic and industrial research groups. This technique allows the various pipelines of a "superscalar" processor to be efficiently utilized by scheduling from several "coarse-grain" threads of one (or several) program(s). Although exploiting both ILP and TLP is attractive, the following questions are investigated in the project:- Can an architecture model, which integrates fine-grain multithreading support with a coarse-grain multithreaded architecture model such as SMT, be developed?- What are the design trade-off when mapping these architecture features to single-chip implementations?- What compiling methodology for the proposed architecture model would exploit thread-level parallelism at both coarse and fine-grain levels?