SHF:Medium:Collaborative Research:Fine-Grain Multithreading through Hardware/Software Co-Design

在过去的15年里，超级计算领域发生了根本性的变化。芯片已经从单线程、单核进化到多线程、多核芯片。即使是主流的高性能芯片也提供接近100个硬件线程。与此同时，具有数百甚至数千个硬件线程的加速器，由于其固有的大规模并行特性，使科学家能够获得某些科学内核的主要性能加速。从软件方面来看，编程语言可以提供一种方法来创建各种类型的并行性，从传统的数据并行结构到细粒度的数据驱动结构：已经添加了指令来利用指令级并行性（ILP），从而允许程序员识别代码何时是可向量化的；加速器友好型指令允许代码在gpu或Intel Xeon Phi处理器上执行；最后，新的关键字使程序员能够表达与任务相关的并行性。为了评估硬件与软件的权衡，研究人员计划设计和开发一个抽象的机器模型，用于可扩展的并行和分布式计算，设计和实现硬件辅助机制来实现它。通过会议和出版物、研讨会以及专门的网站向社区广泛传播研究成果和工具，这项研究有可能在对人类重要的整体和综合解决方案方面培育新的方向。此外，研究人员最近共同创立了IEEE计算机协会的一个特殊技术社区（并行模型和系统），其具体目的是促进美国和世界范围内该领域的研究和教育。该项目旨在开发一种异步细粒度事件驱动程序执行模型，Codelet抽象机模型（CAM），用于并行和分布式系统中的线程管理。研究任务包括对数据流编码模型的三个主要扩展，通过硬件/软件协同设计方法实现CAM，并使用一组基准和应用程序对其进行评估。所提出的基于fpga的原型与通用多核芯片、编译器和运行时系统相结合，目前正在开发的编译器和运行时系统被设计为系统的一部分，允许高级程序员利用最终的系统，目标应用范围从传统的HPC、并行图形处理以及大数据框架。该奖项反映了美国国家科学基金会的法定使命，并通过使用基金会的知识价值和更广泛的影响审查标准进行评估，被认为值得支持。

The supercomputing landscape has fundamentally changed in the past fifteen years. Chips have evolved from single-thread, single-core to multi-threaded, many-core chips. Even mainstream high-performance chips offer close to 100 hardware threads. At the same time, accelerators, featuring hundreds or even thousands of hardware threads, have allowed scientists to obtain major performance speedups for certain classes of scientific kernels, thanks to their inherent massively parallel nature. From the software side, programming languages can provide a way to create various types of parallelism, from traditional data-parallel constructs to fine-grain, data-driven ones: directives have been added to leverage instruction-level parallelism (ILP), thus allowing the programmer to identify when the code is vectorizable; accelerator-friendly directives allow code to execute on GPUs or the Intel Xeon Phi; finally, new keywords enable the programmer to express task-dependent parallelism. In order to evaluate the hardware-software trade-offs, the investigators plan to design and develop an abstract machine model for scalable parallel and distributed computing, designing and implementing hardware-assisted mechanisms to realize it. Through a broad dissemination of the research findings and tools to the community via conferences and publications, seminars, and a dedicated website, this research has the potential to foster new directions in holistic and comprehensive solutions important to humanity. In addition, the investigators have recently co-founded a Special Technical Community (Parallel Models & Systems) of the IEEE Computer Society with the specific purpose of fostering research and education in the domain across US and the world.This project seeks to develop an asynchronous fine-grain event-driven program execution model, Codelet Abstract Machine model (CAM), for thread management in parallel and distributed systems. The research tasks include three major extensions to a dataflow codelet model, implementing CAM by a hardware/software co-design approach and evaluating it using a set of benchmarks and applications. The proposed FPGA-based prototype is built in combination with general-purpose multicore chips and compiler and runtime system currently under development are designed be part of the system to allow high-level programmers to exploit the resulting system targeted to applications ranging from traditional HPC, parallel graph processing, as well as big data frameworks.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.