XPS: FULL: CCA: Collaborative Research: SPARTA: a Stream-based Processor And Run-Time Architecture

XPS：完整：CCA：协作研究：SPARTA：基于流的处理器和运行时架构

• 批准号: 1439165
• 负责人: Jean-Luc Gaudiot
• 金额: $ 27.1万
• 依托单位: University of California-Irvine
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2014
• 资助国家: 美国
• 起止时间: 2014-08-01 至 2018-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1439165&HistoricalAwards=false
• 关键词: XPS; FULL; CCA; Collaborative; Research

Computer systems have undergone a fundamental transformation recently, from single‐core processors to devices with increasingly higher core counts within a single chip. The semi‐conductor industry now faces the infamous power and utilization walls, that is, physical constraints such as levels of power and energy consumption, but also reliability of the various components, must be taken into account not only during the chip fabrication process, but also when generating machine code and during program execution. To meet these challenges, heterogeneity in design, both at the architecture and technology levels, will be the prevailing approach for energy efficient computing as specialized cores, accelerators, and graphical processing units (GPUs) can eliminate the energy overheads of general‐purpose homogeneous cores. However, with future technological challenges pointing in the direction of on‐chip heterogeneity, and because of the traditional difficulty of parallel programming, it becomes imperative to produce new system software stacks that can take advantage of the heterogeneous hardware. This project proposes to rethink the whole hardware‐software interface, by researching novel ways to design many‐core chip architectures and weaving heterogeneous components together and binding them by a fast and energy efficient on‐chip interconnection network. On top of it will lay a system software layer to efficiently drive applications and map them onto the best suited components of the chip. Both the hardware and software layer are encompassed by a novel execution model, which describes how to orchestrate the various parts of a program in the most efficient way (be it with respect to power and energy, performance, or reliability). To achieve these goals, the development of a new model of computation called SPARTA (Stream-based Processor And RunTime Architecture) is proposed. The proposed model combines a new runtime and compiler technology with a hierarchical heterogeneous many‐core chip and features hardware mechanisms for stream‐based fine‐grain program execution models to be reflected in different new software/hardware systems. Many issues are be envisioned, including programmability, scalability, performance evaluation, and power efficiency. Specifically, the goal is to identify the major challenges and obstacles toward an efficient exploitation of parallelism and scalability. To do so, traditional approaches will be re-evaluated by studying a collection of representative programs. A vertical design methodology is then proposed to effectively address the above challenges through the SPARTA approach and its implementation. In particular, the proposed cross-layer methodology consists of (a) a programming/execution model that will combine the Codelet model (leveraging our past research in dataflow models and extensions) with generalized streams: the Streaming Codelets, (b) an architecture model that will efficiently support the Streaming Codelets in heterogeneous hardware, and (c) a system software Stack that will be capable of effectively mapping Streaming Codelets to the proposed architecture. Finally, a qualitative and quantitative study of SPARTA will be performed via selected benchmarks and a consolidated methodology based on experimentation and analysis. The holistic cross-layer design methodology spanning the hardware/software stack and the reliability techniques developed from this research will significantly impact next generation multi‐core and System‐on‐Chip (SoC) architectures with improvements in energy efficiency, programmability, performance and robustness.

计算机系统最近经历了根本性的转变，从单核处理器到单个芯片内具有越来越多的核数的设备。#8208&;导体工业现在面临着臭名昭著的功率和利用壁垒，即，不仅在芯片制造过程期间，而且在生成机器代码和程序执行期间，都必须考虑诸如功率和能量消耗水平的物理约束以及各种组件的可靠性。为了应对这些挑战，在架构和技术层面上的设计异构性将成为节能计算的主流方法，因为专用核、加速器和图形处理单元（GPU）可以消除通用同构核的能量开销。然而，随着未来的技术挑战指向的方向上‐芯片异构性，并且由于并行编程的传统困难，产生可以利用异构硬件的新系统软件栈变得势在必行。该项目提出重新思考整个硬件#8208;软件接口，通过研究新的方法来设计许多#8208;核心芯片架构，并将异构组件编织在一起，并通过快速和节能的芯片互连网络将它们绑定在一起。在它的顶部将放置一个系统软件层，以有效地驱动应用程序，并将它们映射到最适合的芯片组件上。硬件和软件层都包含在一个新的执行模型中，该模型描述了如何以最有效的方式编排程序的各个部分（无论是在功率和能量，性能还是可靠性方面）。为了实现这些目标，提出了一种新的计算模型斯巴达（基于流的处理器和运行时架构）的发展。所提出的模型结合了一个新的运行时和编译器技术与分层异构的许多#8208;核心芯片和功能的硬件机制流#8208;基于精细#8208;颗粒程序执行模型，以反映在不同的新的软件/硬件系统。许多问题是可以预见的，包括可编程性，可扩展性，性能评估，和电源效率。具体来说，目标是确定主要的挑战和障碍，有效地利用并行性和可扩展性。为此，将通过研究一系列有代表性的方案来重新评估传统方法。然后提出了一种垂直设计方法，通过斯巴达方法及其实施有效地解决上述挑战。具体地，所提出的跨层方法包括（a）将结合Codelet模型的联合收割机的编程/执行模型（利用我们过去在Cowllow模型和扩展中的研究）与广义流：流代码片，（B）将有效地支持异构硬件中的流代码片的体系结构模型，以及（c）系统软件栈，其将能够有效地将流代码片映射到所提出的体系结构。最后，将通过选定的基准和以实验和分析为基础的综合方法，对斯巴达进行定性和定量研究。跨硬件/软件堆栈的整体跨层设计方法以及从本研究中开发的可靠性技术将显著影响下一代多核和片上系统（SoC）架构，并在能效、可编程性、性能和鲁棒性方面有所改进。