CAREER: Interconnect-Centric Layout Synthesis and Planning with Consideration of On-Chip Inductance

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This research is on an interconnect-centric layout design methodology incorporating on-chip inductance into the methodology. Specifically, the following problems are explored: (1) accurate modeling and analysis techniques for multiple coupled RLC interconnects; (2) efficient algorithms for interconnect synthesis to optimize performance and signal integrity for coupled RLC nets; (3) efficient algorithms for pre-layout interconnect estimation considering a comprehensive set of interconnect optimization techniques, and application of estimation results to interconnect architecture planning; and (4) efficient algorithms for pre-layout estimation of maximum switching current for functional blocks followed by optimization of the power supply structure using the RLC model. In addition, this project investigates an innovative computer engineering curriculum incorporating interconnect and System-On-Chip (SOC) considerations, and development of Web-based interconnect planning tools for use in innovative teaching and for outreach beyond the campus.