NER: Carbon Nanotube Devices and Integrated Systems

NER：碳纳米管器件和集成系统

• 批准号: 0102955
• 负责人: Chongwu Zhou
• 金额: $ 10万
• 依托单位: University of Southern California
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2001
• 资助国家: 美国
• 起止时间: 2001-06-15 至 2002-11-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0102955&HistoricalAwards=false
• 关键词: NER; Carbon; Nanotube; Devices; Integrated

PROPOSAL NO.: 0102955PRINCIPAL INVESTIGATOR: Zhou, ChongwuINSTITUTION NAME: University of Southern CaliforniaTITLE: NER: Carbon Nanotube Devices and Integrated SystemsThis is a proposal to design, build and evaluate various novel nanotube devices andintegrated systems. Specifically I propose to make n type field effect transistors (FET),nanotube p-n junctions, and an integrated single-molecule CMOS inverter. This researchis exploratory in nature; however, if successful, will advance our understanding of thefundamental properties of nanotubes and produce practical nanoscale devices for the realworld.There has been a great deal of research into carbon nanotubes in the past few years. Ptype field effect transistors have been demonstrated consisting of semiconductivenanotubes with a silicon substrate backgate separated from the tube by a layer of SiO2.Despite the utmost interest in developing n type FETs to enable nanoscale CMOScircuits, the research effort has been hampered by lack of an effective doping method fornanotubes. I propose to demonstrate a simple, effective and reliable method toelectrostatically dope nanotubes into n type, thus paving the way for n type FETs, p-njunctions and integrated systems. This new method will employ TiO2 instead of SiO2 asthe gate dielectric. With a dielectric constant of 30 for TiO2, as compared to 3.8 for SiO2,the gate utilizing TiO2 will be seven times more effective than previously reported, andour preliminary analysis confirms that with a reasonable gate bias (~ 10 V), a nanotubecan be electrostatically doped into n type, thereby producing an n type FETs.Furthermore, carbon nanotube p-n junctions will be demonstrated with a split-gatetechnique, by depositing TiO2 onto a semiconductive nanotube contacted with source anddrain electrodes, and patterning two gate electrodes atop the TiO2, each covering half ofthe tube. By controlling these two gate biases independently, one can tune the left halftube into p type and the right half into n type, thus creating a p-n junction in between,which provides an ideal system for studying the depletion and screening in onedimension.Finally, a simple integrated system will be demonstrated by attaching an electrode to thecenter of a semiconductive nanotube in addition to the source and drain electrodes. Thiscenter electrode divides the nanotube into two segments and serves as the output of thecircuit. The silicon substrate backgate with TiO2 dielectric layer will serve as the circuitinput and be used to tune one tube segment to function as an n type FET and the othersegment as a p type FET, thereby forming the worlds first single molecule inverter.

提案编号： 0102955主要负责人：周崇武机构名称：南加州大学标题：NER：碳纳米管器件和集成系统这是一个设计，建造和评估各种新型纳米管器件和集成系统的建议。具体来说，我建议制作n型场效应晶体管（FET），纳米管p-n结，和集成的单分子CMOS反相器。这项研究本质上是探索性的;然而，如果成功的话，将促进我们对纳米管基本性质的理解，并为现实世界生产实用的纳米器件。在过去的几年里，人们对碳纳米管进行了大量的研究。P型场效应晶体管由纳米管和硅衬底背栅组成，背栅与管之间由一层SiO2隔开。尽管人们对开发n型场效应晶体管以实现纳米CMOS电路非常感兴趣，但由于缺乏有效的纳米管掺杂方法，研究工作受到阻碍。我提出了一种简单、有效和可靠的方法，将纳米管静电掺杂到n型中，从而为n型FET、p-n结和集成系统铺平了道路。这种新方法将采用TiO 2代替SiO 2作为栅介质。当TiO 2的介电常数为30时，与SiO2的介电常数为3.8时相比，利用TiO 2的栅极将比先前报道的有效7倍，并且我们的初步分析证实，在合理的栅极偏压（~ 10 V）下，纳米管可以静电掺杂成n型，从而产生n型FET。通过将TiO 2沉积到与源极和漏极接触的纳米管上，并在TiO 2顶部图案化两个栅极，每个栅极覆盖管的一半。通过独立控制这两个栅极偏压，可以将左半管调谐为p型，右半管调谐为n型，从而在两者之间形成p-n结，这为一维研究耗尽和屏蔽提供了一个理想的系统。最后，将一个简单的集成系统通过在源极和漏极之外附加一个电极到纳米管的中心来演示。这个中心电极将纳米管分成两段，并作为电路的输出。具有TiO 2介电层的硅衬底背栅将用作电路输入，并用于调谐一个管段以用作n型FET，另一个管段用作p型FET，从而形成世界上第一个单分子反相器。