CAREER: INVESTIGATING ELECTROSTATIC DISCHARGE PROTECTION IN ULSI ICs DOWN TO NANO-SCALE: SIMULATION, MODELING & EXPERIMENTS

静电放电(ESD)失效是VDSM(Very-深亚微米)和纳米级SiULSI集成电路工艺的毁灭性可靠性问题。必须研究ESD失效的基本原理和片上ESD保护理论，重点研究以下挑战：3D混合模式ESD模拟方法；精确的大电流ESD建模；全芯片ESD设计综合；用于ULSI IC的先进的ESD保护解决方案；超GHz射频IC的ESD保护；纳米级和宽带隙半导体IC技术的ESD保护。PI提出了一项应对这些挑战的职业发展计划。拟议的研究活动包括六项任务：通过开发一种新颖的3D混合模式ESD模拟方法来研究ULSI IC中先进的片上ESD保护现象；通过开发准确的大电流ESD器件模型来研究ESD保护基础；开发名为ESDCAT的全芯片ESD设计验证CAD工具；探索用于亚100 nm ULSI IC的新型超高速ESD保护解决方案；探索未来纳米技术的ESD保护；以及将ESD研究扩展到超GHz射频IC和宽带隙半导体GaN。由于ESD现象是几何相关的，涉及复杂的电热工艺器件电路耦合，所提出的研究方法采用全尺度混合模式方法，以3D格式研究全耦合工艺-器件-电路-电子-热闭合回路中的ESD基本原理。为实现大电流ESD的精确建模，提出了一种三维并行ESD模型网络。ESDCAT支持原理图和版图级别的芯片级ESD综合和验证。纳米尺度的ESD研究将考虑弹道声子散射效应。用于宽带隙的ESD将集中在与硅兼容的GaN集成电路上。最终结果包括对ESD机制的洞察，以及用于进一步研究和设计各种IC技术的ESD保护的CAD工具，例如，CMOS、BiCMOS、SOI、SiGe、GaN、RFIC和铜互连。新的ESD理论和立即的工业应用都有望实现。教育计划的核心是：新课程开发；微电子研究与教育的整合；学生辅导和社区服务；以及大学与产业合作。具体来说，活动包括：在五年内开发五门课程/实验室；改进微电子教学方法；建立综合电子实验室、虚拟集成电路制造设施和TCAD/ECAD设计工作室；为学生开展跨专业项目提供建议；制定本科生产业合作计划；让少数族裔/女性学生参与微电子研究。这项为期五年的教育计划已纳入微电子系的再发展计划。

Electrostatic Discharge (ESD) failure is a devastating reliability problem to VDSM (very-deep-sub-micron) and nano-scale Si ULSI IC technologies. It is imperative to investigate ESD failure fundamentals and on-chip ESD protection theories focusing on the following challenges: 3D mixed-mode ESD simulation methodology; accurate high-current ESD modeling; whole-chip ESD design synthesis, advanced ESD protection solutions for ULSI ICs, ESDprotection for super-GHz RF ICs, ESD protection for nano-scale as well as wide-bandgap semiconductor IC technologies. The PI proposes a career development plan that addresses these challenges.Proposed research activities consist of six tasks: to investigate advanced on-chip ESD protection phenomena in ULSI ICs by developing a novel 3D mixed-mode ESD simulation methodology; to investigate ESD protection fundamentals by developing accurate high-current ESD device models; to develop a full-chip ESD design verification CAD tool called ESDcat; to explore novel ultra-fast ESD protection solutions for sub-100nm ULSI ICs, to explore ESD protection for future nano-technologies, and to extend ESD research to super-GHz RF ICs and wide-bandgap semiconductor, GaN. Since ESD phenomena are geometry-dependent involving complex electro-thermal-process-device-circuit coupling, the proposed research procedures take full-scale mixed-mode approaches that investigate ESD fundamentals in a fully-coupled process-device-circuit-electronic-thermal closed-loop in 3D format. A 3D parallel ESD model network is proposed for accurate high-current ESD modeling. ESDcat enables chip level ESD synthesis and verification at both schematic and layout levels. Nano-scale ESD research will take into account the ballistic phonon scattering effect. ESD for wide-bandgaps will focus on Si-compatible GaN ICs. End results include insights into ESD mechanisms, CAD tools for further investigation and design of ESD protections for various IC technologies, e.g., CMOS, BiCMOS, SOI, SiGe, GaN, RFIC, and Cu interconnects. Both new ESD theory and immediate industrial applications are expected.The education plan centers on: new curriculum development; integration of microelectronics research and education; student mentoring and community services; and university-industry collaboration. Specifically, activities include: develop five courses/labs in a five-year period; pursue an improved microelectronics teaching approach; establish an Integrated Electronics Laboratory, a Virtual IC Fab facility, and TCAD/ECAD Design Studios; advising students in conducting inter-professional projects; develop a undergraduate industrial co-op program; and involving minority/women students in microelectronics research. This five-year education proposal is integrated into the departmental redevelopment plan in microelectronics