NANOWIRE CROSSBAR SWITCH ESD PROTECTION MECHANISM AND CIRCUIT

纳米线交叉开关ESD保护机制和电路

• 批准号: 0701687
• 负责人: Albert Wang
• 金额: $ 27万
• 依托单位: Illinois Institute of Technology
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2007
• 资助国家: 美国
• 起止时间: 2007-05-01 至 2008-02-29
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0701687&HistoricalAwards=false
• 关键词: NANOWIRE; CROSSBAR; SWITCH; ESD; PROTECTION

The objective of this research is to develop non-traditional Electrostatic Discharge (ESD) protection mechanisms and structures, using novel nanowire crossbar array and nano mechanical switch mechanisms, for nanoscale integrated circuits (IC). The approach is to investigate new nanowire switching ESD discharging mechanism, to fabricate and characterize nano crossbar switch arrays, to explore CMOS-compatible fabrication flow and to develop new modeling techniques.Intellectual Merits: ESD failure is the most devastating IC reliability problem in sub-100nm regime that causes the industry billions of dollars annually. On-chip ESD protection is hence required to protect ICs against ESD damage. ESD failure and protection involves very complex multi-coupling effects. As IC technologies continue to shrink, ESD-induced leakage and mis-triggering effect at GHz operation, inherent to its traditional transistor-type protection mechanism, become intolerable. It is hence imperative to develop novel ESD protection mechanisms and structures. This project is to develop completely new nanowire crossbar array and nano mechanical switch based ESD protection mechanisms and structures, which intends to replace the decade-long traditional ESD protection mechanism, therefore to eliminate the ESD-induced leakage and mis-triggering problems. Broader Impacts: Success of this project will deliver the first nanowire crossbar array and nano mechanical switch ESD protection mechanisms and structures for next generation IC technologies at nanoscale. The new ESD protection solutions are critical to finally resolving the grand IC reliability challenge at nano nodes. NSF support of this research enables the proposed international-academia-industry collaboration activities that greatly benefit American students, the semiconductor industry, the academia and the American society.

本研究的目的是开发用于纳米级集成电路（IC）的非传统静电放电（ESD）保护机制和结构，采用新型纳米线交叉棒阵列和纳米机械开关机制。该方法旨在研究新型纳米线开关ESD放电机理，制备和表征纳米交叉棒开关阵列，探索cmos兼容的制造流程并开发新的建模技术。知识优势：ESD故障是亚100nm制程中最具破坏性的IC可靠性问题，每年给业界造成数十亿美元的损失。因此，需要片内ESD保护来保护ic免受ESD损坏。ESD失效与保护涉及到非常复杂的多耦合效应。随着集成电路技术的不断缩小，传统晶体管型保护机制固有的GHz工作条件下的esd诱发漏电和误触发效应变得难以忍受。因此，开发新的ESD保护机制和结构势在必行。本项目是开发全新的基于纳米线交叉棒阵列和纳米机械开关的ESD保护机制和结构，旨在取代已有十年之久的传统ESD保护机制，从而消除静电引起的漏电和误触发问题。更广泛的影响：该项目的成功将为下一代纳米级集成电路技术提供第一个纳米线交叉棒阵列和纳米机械开关ESD保护机制和结构。新的ESD保护解决方案对于最终解决纳米节点IC可靠性的重大挑战至关重要。美国国家科学基金会对这项研究的支持使拟议的国际学术界和工业界合作活动大大受益于美国学生，半导体行业，学术界和美国社会。