Reliability Analysis and Robust Synthesis of HIgh-Performance Clock Networks.

该提案的研究部分是探索时钟网络的新方法，明确说明各种设计因素之间的相互作用。教育部分将为研究生研究人员提供VLSI，优化和数值计算方面的跨学科培训。此外，研究成果将被纳入普渡大学的研究生课程。时钟网络的设计是同步电路合成中的一个基本问题，需要在设计努力、物理资源成本和性能之间进行权衡。大多数现有的时钟设计方法都没有明确地执行这种权衡。相反，首先提出设计，然后根据物理资源成本和性能评估设计，必要时重复设计。由于可能需要大量这样的迭代，因此通过一些简化的假设可以将设计工作最小化。这些人为强加的约束之一是“零偏差”，即要求所有元素在同一时间瞬间被计时（即开关）。这一要求限制了时钟分配网络的物理布局，因为时钟信号到达各个开关元件时的变化必须保持小。也许更重要的是，当所有电路元件一起切换时，来自电源的需求在一段时间内并不均匀，而是在每个时钟周期内急剧达到峰值。这种对电源的不均匀需求导致了通常所说的电源噪声：当对电源的需求急剧达到峰值时，其提供功率的能力就会下降，从而可能导致电路性能下降。以这些观察结果为背景，我们建议开发一种采用非零时钟偏差的时钟网络设计方法，并直接解决决定设计努力、物理资源成本和性能之间权衡的各种因素之间的相互作用。我们提出的初步结果表明，我们的方法很有希望。具体而言，我们建议将时钟网络的调度和合成一起进行，从而降低电源噪声和物理资源成本。电源噪声的有效分析对我们的目标至关重要。我们提出了电源噪声分析的框架和技术，该框架和技术借鉴了我们过去在时域和频域中互连建模的模型简化技术的成功经验。

The research component of the proposal is to explore a new methodology for clock networks that explicitly accounts for the interplay between the various design factors. The educational component will provide graduate student researchers with an interdisciplinary training in VLSI, optimization, and numerical computing. Furthermore, the research results will be integrated in graduate courses at Purdue University.The design of clock networks is a fundamental problem in synchronous circuit synthesis, and requires trading off between design effort, physical resource costs and performance. Most existing clock design methodologies do not explicitly perform this trade-off. Instead, a design is first proposed, and then evaluated in terms of physical resource costs and performance, and the design repeated if necessary. As a large number of such iterations may be required, the design effort is minimized with some simplifying assumptions. One of these artificially imposed constraints is that of ``zero-skew'', where it is required that all elements are clocked (i.e., switch) at the same time-instant. This requirement constrains the physical layout of clock distribution networks, as the variation in the arrival of the clock signal at the various switching elements must be held small. Perhaps more important, as all circuit elements switch together, the demand from the power supply is not uniform over time but peaks sharply once every clock cycle. This uneven demand on the power supply leads to what is commonly referred to as power-supply noise: As the demands on the power supply peak sharply, its ability to deliver power degrades, leading to possibly degraded performance of the circuits.With these observations serving as the backdrop, we propose to develop a design methodology for clock networks that employs nonzero clock skews, and directly addresses the interplay between various factors that determine the trade-off between the design effort, physical resource costs and performance. We present preliminary results that show that our approach holds much promise. Specifically, we propose to perform together scheduling and synthesis of clock networks such that both power supply noise and physical resource costs are reduced. Essential to our objectives is the efficient analysis of power supply noise. We propose a framework and techniques for power-supply noise analysis that draw upon our past successes with model reduction techniques for interconnect modeling both in the time and frequency domain.