Reliability Analysis and Robust Synthesis of HIgh-Performance Clock Networks.

高性能时钟网络的可靠性分析和鲁棒综合。

• 批准号: 0203362
• 负责人: Cheng-Kok Koh
• 金额: $ 24万
• 依托单位: Purdue University
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-07-01 至 2006-12-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0203362&HistoricalAwards=false
• 关键词: Reliability; Analysis; Robust; Synthesis; Performance

The research component of the proposal is to explore a new methodology for clock networks that explicitly accounts for the interplay between the various design factors. The educational component will provide graduate student researchers with an interdisciplinary training in VLSI, optimization, and numerical computing. Furthermore, the research results will be integrated in graduate courses at Purdue University.The design of clock networks is a fundamental problem in synchronous circuit synthesis, and requires trading off between design effort, physical resource costs and performance. Most existing clock design methodologies do not explicitly perform this trade-off. Instead, a design is first proposed, and then evaluated in terms of physical resource costs and performance, and the design repeated if necessary. As a large number of such iterations may be required, the design effort is minimized with some simplifying assumptions. One of these artificially imposed constraints is that of ``zero-skew'', where it is required that all elements are clocked (i.e., switch) at the same time-instant. This requirement constrains the physical layout of clock distribution networks, as the variation in the arrival of the clock signal at the various switching elements must be held small. Perhaps more important, as all circuit elements switch together, the demand from the power supply is not uniform over time but peaks sharply once every clock cycle. This uneven demand on the power supply leads to what is commonly referred to as power-supply noise: As the demands on the power supply peak sharply, its ability to deliver power degrades, leading to possibly degraded performance of the circuits.With these observations serving as the backdrop, we propose to develop a design methodology for clock networks that employs nonzero clock skews, and directly addresses the interplay between various factors that determine the trade-off between the design effort, physical resource costs and performance. We present preliminary results that show that our approach holds much promise. Specifically, we propose to perform together scheduling and synthesis of clock networks such that both power supply noise and physical resource costs are reduced. Essential to our objectives is the efficient analysis of power supply noise. We propose a framework and techniques for power-supply noise analysis that draw upon our past successes with model reduction techniques for interconnect modeling both in the time and frequency domain.

该提案的研究部分是探索一种新的时钟网络方法，明确说明各种设计因素之间的相互作用。 教育部分将为研究生研究人员提供VLSI，优化和数值计算的跨学科培训。 此外，研究成果将被整合到普渡大学的研究生课程中。时钟网络的设计是同步电路综合中的一个基本问题，需要在设计工作量、物理资源成本和性能之间进行权衡。 大多数现有的时钟设计方法并没有明确地执行这种权衡。 相反，首先提出设计，然后根据物理资源成本和性能进行评估，必要时重复设计。由于可能需要大量的此类迭代，因此可以通过一些简化的假设来最大限度地减少设计工作量。 这些人为施加的约束之一是“零偏斜”，其中要求所有元件都被计时（即，开关），在同一时间。 这个要求限制了时钟分配网络的物理布局，因为时钟信号到达各个开关元件的变化必须保持很小。也许更重要的是，由于所有电路元件都在一起切换，因此电源的需求随时间变化并不均匀，而是在每个时钟周期出现一次急剧的峰值。 这种对电源的不均匀需求导致了通常所说的电源噪声：随着对电源的需求急剧上升，其提供功率的能力下降，导致电路的性能可能下降。以这些观察为背景，我们建议开发一种采用非零时钟偏差的时钟网络的设计方法，并且直接解决了确定设计工作、物理资源成本和性能之间的折衷的各种因素之间的相互作用。 我们目前的初步结果表明，我们的方法有很大的希望。具体来说，我们建议一起执行调度和时钟网络的合成，这样既降低了电源噪声和物理资源成本。 对我们的目标至关重要的是电源噪声的有效分析。 我们提出了一个框架和技术的电源噪声分析，借鉴我们过去的成功与模型简化技术的互连建模在时域和频域。