Career: Interconnect Planning and Synthesis of Physical Layout for Deep Submicron VLSI Design

随着VLSI技术的不断扩展，互连在决定系统性能、功耗、可靠性和成本方面发挥着主导作用。为了确保设计的定时关闭，必须在每个设计阶段考虑互连的影响。这项研究旨在开发一种以互连为中心的设计方法，强调在物理设计流程中的互连规划和综合。根据这笔赠款开展的研究活动包括：(A)开发可布线性驱动的中继器规划算法，用于在布线规划和布局过程中优化多个全局网络；(B)开发新的版图合成技术--拓扑结构、导线尺寸/分割和间距以及中继器插入--用于优化片上RLC互连的互连延迟和信号完整性；(C)开发同时执行多个网络的布线和专用电流返回路径合成的全局布线算法；(D)开发可靠的时钟合成技术，将与电路开关活动相关的电流感应噪声的风险降至最低。

With the continued scaling of VLSI technologies, interconnects play a dominant role in determining system performance, power, reliability, and cost. To ensure timing closure of designs, impacts of interconnects must be considered at every design stage. This research is directed at developing an interconnect-centric design methodology that emphasizes interconnect planning and synthesis during physical design flow. Research activities being carried out under this grant include: (a) Developing routability-driven repeater planning algorithms for the optimization of multiple global nets during floorplanning and placement; (b) Developing novel layout synthesis techniques -- topology construction, wire-sizing/splitting and spacing, and repeater insertion -- for the optimization of interconnect delay and signal integrity of on-chip RLC interconnects; (c) Developing global routing algorithms that perform simultaneously the routing of multiple nets and the synthesis of dedicated current return paths; (d) Developing reliable clock synthesis techniques that minimize the risk of current induced noise associated with the switching activities of circuits.