Career: Interconnect Planning and Synthesis of Physical Layout for Deep Submicron VLSI Design

随着超大规模集成电路技术的不断发展，互连线在决定系统性能、功耗、可靠性和成本方面起着主导作用。为了保证设计的时序收敛性，在每个设计阶段都必须考虑互连线的影响。本研究旨在发展一种以互连为中心的设计方法，强调在物理设计流程中的互连规划和综合。利用该赠款进行的研究活动包括：（a）开发可布线性驱动的中继器规划算法，以便在平面规划和布局期间优化多个全局网络;（B）开发新的布局综合技术-拓扑结构、导线尺寸/分裂和间隔以及中继器插入-以便优化片上RLC互连的互连延迟和信号完整性;（c）开发全局布线算法，同时执行多个网络的布线和专用电流返回路径的合成;（d）开发可靠的时钟合成技术，最大限度地减少与电路开关活动有关的电流感应噪声的风险。

With the continued scaling of VLSI technologies, interconnects play a dominant role in determining system performance, power, reliability, and cost. To ensure timing closure of designs, impacts of interconnects must be considered at every design stage. This research is directed at developing an interconnect-centric design methodology that emphasizes interconnect planning and synthesis during physical design flow. Research activities being carried out under this grant include: (a) Developing routability-driven repeater planning algorithms for the optimization of multiple global nets during floorplanning and placement; (b) Developing novel layout synthesis techniques -- topology construction, wire-sizing/splitting and spacing, and repeater insertion -- for the optimization of interconnect delay and signal integrity of on-chip RLC interconnects; (c) Developing global routing algorithms that perform simultaneously the routing of multiple nets and the synthesis of dedicated current return paths; (d) Developing reliable clock synthesis techniques that minimize the risk of current induced noise associated with the switching activities of circuits.