ITR: Decentralized Streaming Architecture (DSA) for High Capacity Systems

传统的计算机体系结构一直基于和主导的能力差的系统，我们被迫建立20和50年前。 三十多年来，指令集体系结构（伊萨）已经形成了可扩展性的基本体系结构抽象。 尽管ISA抽象很棒，但它的实用范围即将结束。 我们的系统在规模和速度上都有了数量级的增长，伊萨的许多简化假设限制了向前的可扩展性，而不是使其成为可能。 这项工作探索了我们的基本假设和机器抽象的公式化，以适应我们现在可以构建的大容量计算系统。 当原始指令序列是ISA模型中的核心固定点时，本文提出流连接图作为这些分散流架构（DSA）的模型固定点。 这种方式直接在体系结构中抽象通信，促进了并行性和物理局部性的优化. DSA将为未来的计算系统提供一个单一的、统一的系统模型，这些计算系统可以从小型的单芯片、单处理器系统扩展到多处理器IC，再到各种异构的片上系统设计，再到大规模的、异构的、多组件的系统，这些系统将在十年的生命周期内不断发展。

Conventional computer architecture has been based on and dominated by thecapacity poor systems we were forced to build 20 and 50 years ago. Forover three decades, the Instruction Set Architecture (ISA) has formed thebasic architectural abstraction for scalability. As wonderful as the ISAabstraction has been, its range of utility is coming to an end. Oursystems have grown orders of magnitude in size and speed, and many of thesimplifying assumptions which underly the ISA are limiting forwardscalability rather than enabling them. This effort explores areformulation of our basic assumptions and machine abstractions toaccommodate the large capacity computing systems we can now build. Whereasthe sequence of primitive instructions was the core fixed point in ISAmodel, this effort proposes stream-connected graphs as the model fixedpoint for these Decentralized Streaming Architectures (DSA). This waycommunication is abstracted directly in the architecture facilitatingparallelism and optimization for physical locality. DSA will give us asingle, unifying system model for future computing systems which scalesfrom modest, single-chip, single-processor systems, to multiprocessor ICs,to a wide range of heterogeneous System-on-a-Chip designs, to large-scale,heterogeneous, multi-component systems that evolve over decade longlifecycles.