CAREER: Interconnect Design for Programmable Computation

职业：可编程计算互连设计

• 批准号: 0133102
• 负责人: Andre DeHon
• 金额: $ 37.5万
• 依托单位: California Institute of Technology
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-04-01 至 2007-05-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0133102&HistoricalAwards=false
• 关键词: CAREER; Interconnect; Design; Programmable; Computation

Interconnect has always been the dominant component consuming area, delay, and energy in Field-Programmable Gate Arrays and related spatial computing devices. With interconnect requirements scaling faster than linearly in device gate capacity and fundamental interconnect delays in VLSI scaling slower than gate speeds, this problem is only exacerbated as we go forward. Further, with the size of silicon systems we can build today, all kinds of single-chip architectures (e.g. multiprocessor, system-on-a-chip, VLIW, Vector, PIM) will be moving toward greater on-chip parallelism and hence greater use of on-chip, programmable interconnect.Nonetheless, interconnect is probably the least understood component in programmable devices. The fundamental goal of this research is to close gaps in our understanding of interconnect structures and in our quantification of interconnect requirements and synthesize this understanding into an engineering-grade approach to programmable interconnect design. This effort will build upon results in VLSI and Parallel theory, but goes beyond them to close asymptotic gaps, understand how to optimize the constant factors, and characterize the properties and behavior of typical designs. The pedagogical goal is to make the design space, issues, tradeoffs, and impact of spatial interconnect design accessible to students and practitioners with an undergraduate computer science background.

在现场可编程门阵列和相关的空间计算设备中，互连一直是消耗面积、延迟和能量的主要部件。随着互连要求在器件栅极容量上比线性缩放更快，并且在VLSI缩放中的基本互连延迟比栅极速度慢，这个问题只会随着我们的前进而加剧。 此外，随着我们今天可以构建的硅系统的大小，所有类型的单芯片架构（例如多处理器，片上系统，VLIW，Vector，PIM）将朝着更大的片上并行性发展，因此更多地使用片上可编程互连。 这项研究的基本目标是缩小我们对互连结构的理解和对互连要求的量化方面的差距，并将这种理解综合成一个 可编程互连设计的工程级方法。 这项工作将建立在超大规模集成电路和并行理论的结果，但超越他们关闭渐近差距，了解如何优化常数因子，并表征典型设计的属性和行为。教学目标是使设计空间，问题，权衡和空间互连设计的影响，学生和从业人员与本科计算机科学背景。