ITR: Code and Data Segment Optimizations for Mixed Width Instruction Set Embedded Processors

ITR：混合宽度指令集嵌入式处理器的代码和数据段优化

• 批准号: 0220262
• 负责人: Santosh Pande
• 金额: --
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2002
• 资助国家: 美国
• 起止时间: 2002-08-01 至 2008-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0220262&HistoricalAwards=false
• 关键词: ITR; Code; Data; Segment; Optimizations

AbstractThe ARM processor, a leading processor design for the embedded domain, supports a 32 bit ARM instruction set as well as a 16 bit Thumb instruction set. This project is aimed at exploring two approaches for generating code that will simultaneously achieve the goals of small code size, low energy consumption, and good performance. The first approach judiciously combines the use of ARM and Thumb instructions to generate mixed code either dynamically or at compile time. The second approach focusses on changing the data and code layout in a way that compact code can be generated without sacrifcing good performance. To thoroughly explore the above approaches an experimental infrastructure based upon the Simplescalar simulator and the gcc compiler is being developed.

ARM处理器是嵌入式领域的一种主流处理器，它支持32位ARM指令集和16位Thumb指令集。该项目旨在探索两种生成代码的方法，同时实现小代码大小，低能耗和良好性能的目标。第一种方法明智地结合了ARM和Thumb指令的使用，以动态或在编译时生成混合代码。第二种方法侧重于更改数据和代码布局，以生成紧凑的代码，而无需获得良好的性能。 为了彻底探索上述方法的基础上Simplescalar模拟器和GCC编译器的实验基础设施正在开发中。