Compiler Optimizations for Network Processors

网络处理器的编译器优化

• 批准号: 0541273
• 负责人: Santosh Pande
• 金额: $ 27.5万
• 依托单位: Georgia Tech Research Corporation
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-04-01 至 2009-03-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541273&HistoricalAwards=false
• 关键词: Compiler; Optimizations; Network; Processors

Network processors are designed as application specific processors to perform the packet processing at very high line speeds. Network processors are geared towards achieving both fast processing speed and allowing flexibility of programming. Achieving high processing speed as well as providing enough programmability has led to the peculiar architectural design of network processors which is clocked at very high frequencies to match the line speeds. The architecture of network processors considers many special properties for packet processing, including multiple threads, multi-processing, special functional units, dual bank register files, simplified ISA and simplified pipeline, etc. The architectural peculiarities of network processors raise new challenges for compiler design. It is particularly important for the compiler to generate optimized code that could make best use of the architecture features without imposing a heavy burden on the programmer. In addition, unique needs of network processing applications (such as real time response needs etc.) tend to add more burden on the programmers and compiler writers. This could serve as a barrier to the wide scale deployment of applications on these processors. Newer packet processing requirements for intrusion analysis, QoS, traffic analysis etc. in fact demand more and more functionalities to be fulfilled during routing and therefore such barriers must be removed. In this work, it is proposed to develop compiler optimizations for Intel IXP 1200/2400/2800 series. It is believed that the proposed work will solve major problems that pose major barriers currently: how to infuse the application behavior into optimization decisions without jeopardizing the programmability and how to perform aggressive optimizations to deploy these applications in a system wide setting that work at high line speeds. The optimizations will be extensively tested in a real system on real system wide applications.

网络处理器被设计为专用处理器，以非常高的线路速度执行分组处理。网络处理器旨在实现快速处理速度和编程灵活性。实现高处理速度以及提供足够的可编程性导致了网络处理器的特殊架构设计，其以非常高的频率进行时钟控制以匹配线速度。网络处理器的体系结构考虑了包处理的许多特殊性质，包括多线程、多处理、特殊功能单元、双组寄存器文件、简化伊萨和简化流水线等。网络处理器体系结构的特殊性给编译器设计提出了新的挑战。对于编译器来说，生成优化的代码是特别重要的，这些代码可以最好地利用体系结构的特性，而不会给程序员带来沉重的负担。此外，网络处理应用的独特需求（例如真实的时间响应需求等）往往会给程序员和编译器编写者增加更多的负担。这可能成为在这些处理器上大规模部署应用程序的障碍。入侵分析、QoS、流量分析等较新的数据包处理要求实际上要求在路由期间实现越来越多的功能，因此必须消除这些障碍。在这项工作中，它提出了开发英特尔IXP 1200/2400/2800系列的编译器优化。据信，所提出的工作将解决目前构成主要障碍的主要问题：如何将应用程序行为注入优化决策而不危及可编程性，以及如何执行积极的优化，以部署这些应用程序在系统范围内的设置，工作在高线速度。优化将在真实的系统中在真实的系统范围的应用中进行广泛的测试。