Compiler Optimizations for Network Processors

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Network processors are designed as application specific processors to perform the packet processing at very high line speeds. Network processors are geared towards achieving both fast processing speed and allowing flexibility of programming. Achieving high processing speed as well as providing enough programmability has led to the peculiar architectural design of network processors which is clocked at very high frequencies to match the line speeds. The architecture of network processors considers many special properties for packet processing, including multiple threads, multi-processing, special functional units, dual bank register files, simplified ISA and simplified pipeline, etc. The architectural peculiarities of network processors raise new challenges for compiler design. It is particularly important for the compiler to generate optimized code that could make best use of the architecture features without imposing a heavy burden on the programmer. In addition, unique needs of network processing applications (such as real time response needs etc.) tend to add more burden on the programmers and compiler writers. This could serve as a barrier to the wide scale deployment of applications on these processors. Newer packet processing requirements for intrusion analysis, QoS, traffic analysis etc. in fact demand more and more functionalities to be fulfilled during routing and therefore such barriers must be removed. In this work, it is proposed to develop compiler optimizations for Intel IXP 1200/2400/2800 series. It is believed that the proposed work will solve major problems that pose major barriers currently: how to infuse the application behavior into optimization decisions without jeopardizing the programmability and how to perform aggressive optimizations to deploy these applications in a system wide setting that work at high line speeds. The optimizations will be extensively tested in a real system on real system wide applications.