ITR: Code and Data Segment Optimizations for Mixed Width Instruction Set Embedded Processor
ITR: Code and Data Segment Optimizations for Mixed Width Instruction Set Embedded Processor
批准号:
0220334
负责人:
Rajiv Gupta
金额:
$14.91万
依托单位:
依托单位国家:
美国
项目类别:
Continuing Grant
财政年份:
2002
资助国家:
美国
项目状态:
已结题
起止时间:
2002-08-01 至 2005-07-31
中文摘要
点击翻译按钮获取中文摘要
英文摘要
The ARM processor, a leading processor design for the embedded domain, supports a 32 bit ARM instruc-tion set as well as a 16 bit Thumb instruction set. This project is aimed at exploring two approaches for generating code that will simultaneously achieve the goals of small code size, low energy consumption, and good performance. The frst approach judiciously combines the use of ARM and Thumb instructions to generate mixed code either dynamically or at compile time. The second approach focusses on changing the data layout in a way that compact code can be generated without sacrifcing good performance. To thoroughly explore the above approaches an experimental infrastructure based upon the Simplescalar simulator and the gcc compiler is being developed.
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