SHF: Small: Memory Consistency -- Hardware, Compiler, and Programming Support

SHF：小：内存一致性——硬件、编译器和编程支持

• 批准号: 1318103
• 负责人: Rajiv Gupta
• 金额: $ 45万
• 依托单位: University of California-Riverside
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1318103&HistoricalAwards=false
• 关键词: SHF; Small; Memory; Consistency; Hardware

The advent of multicore machines has enabled delivery of high performance via parallelism for a wide range of applications. While such machines have become ubiquitous, they pose significant challenges for software developers. One challenge is dealing with the relaxed memory consistency models supported by commercial multicore machines. Simultaneously delivering high performance and ensuring program correctness requires careful introduction of fence instructions in the code. Excessive use of fence instructions leads to poor performance while their omission of can lead to incorrect program behavior.This research will investigate means for constraining the scope of a fence instruction to minimize its impact on performance while preserving desired program behavior. In existing systems the hardware is unaware of the scope and hence fence implementations enforce a strict ordering of memory accesses across a fence that leads to unnecessary stalls. Alternative means for inferring the scope information will be developed for constraining the memory orderings enforced by the hardware. In particular, development of hardware, compiler, and programming support will be carried out. The software and hardware techniques developed in this research will be made available so other researchers are able to experiment with them. The subject of research is relevant to commercial processor manufacturers. The students involved in this research will receive valuable training in the design and programming of multicore systems.

多核机器的出现使得能够通过并行性为广泛的应用提供高性能。虽然这种机器已经变得无处不在，但它们对软件开发人员构成了重大挑战。一个挑战是处理商业多核机器支持的宽松内存一致性模型。要同时提供高性能和确保程序正确性，需要在代码中仔细引入栅栏指令。过度使用栅栏指令会导致性能低下，而忽略栅栏指令则会导致程序行为不正确。本研究将探讨如何限制栅栏指令的范围，以最大限度地减少其对性能的影响，同时保持所需的程序行为。在现有系统中，硬件不知道范围，因此围栏实现强制执行跨围栏的存储器访问的严格排序，这导致不必要的停顿。将开发用于推断范围信息的替代手段，以约束由硬件执行的存储器排序。特别是，将进行硬件、编译器和编程支持的开发。在这项研究中开发的软件和硬件技术将被提供，以便其他研究人员能够进行实验。研究的主题与商业处理器制造商有关。参与这项研究的学生将在多核系统的设计和编程方面接受有价值的培训。