SHF: Small: Memory Consistency -- Hardware, Compiler, and Programming Support

SHF：小：内存一致性——硬件、编译器和编程支持

• 批准号: 1318103
• 负责人: Rajiv Gupta
• 金额: $ 45万
• 依托单位: University of California-Riverside
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2013
• 资助国家: 美国
• 起止时间: 2013-09-01 至 2017-08-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=1318103&HistoricalAwards=false
• 关键词: SHF; Small; Memory; Consistency; Hardware

The advent of multicore machines has enabled delivery of high performance via parallelism for a wide range of applications. While such machines have become ubiquitous, they pose significant challenges for software developers. One challenge is dealing with the relaxed memory consistency models supported by commercial multicore machines. Simultaneously delivering high performance and ensuring program correctness requires careful introduction of fence instructions in the code. Excessive use of fence instructions leads to poor performance while their omission of can lead to incorrect program behavior.This research will investigate means for constraining the scope of a fence instruction to minimize its impact on performance while preserving desired program behavior. In existing systems the hardware is unaware of the scope and hence fence implementations enforce a strict ordering of memory accesses across a fence that leads to unnecessary stalls. Alternative means for inferring the scope information will be developed for constraining the memory orderings enforced by the hardware. In particular, development of hardware, compiler, and programming support will be carried out. The software and hardware techniques developed in this research will be made available so other researchers are able to experiment with them. The subject of research is relevant to commercial processor manufacturers. The students involved in this research will receive valuable training in the design and programming of multicore systems.

多核机器的出现使得通过并行为广泛的应用程序提供高性能成为可能。虽然这样的机器已经变得无处不在，但它们给软件开发人员带来了巨大的挑战。其中一个挑战是处理商业多核机器支持的宽松内存一致性模型。在提供高性能和确保程序正确性的同时，需要在代码中仔细引入防护指令。过度使用围栏指令会导致性能下降，而忽略围栏指令会导致不正确的程序行为。本研究将研究限制围栏指令范围的方法，以最大限度地减少其对性能的影响，同时保留所需的程序行为。在现有系统中，硬件不知道作用域，因此栅栏实现对跨越栅栏的内存访问强制严格排序，从而导致不必要的停顿。将开发用于推断作用域信息的替代手段，以约束由硬件实施的存储器排序。特别是，将进行硬件、编译器和编程支持的开发。在这项研究中开发的软件和硬件技术将可用，以便其他研究人员能够进行实验。研究的主题与商业处理器制造商有关。参与这项研究的学生将在多核系统的设计和编程方面接受宝贵的培训。