ITR: Exposing the compiler to the hardware: Memory Subsystem Optimizations through Compiler/Micro-architecture Cooperation using Set Membership Information and Color Sets

ITR：将编译器暴露给硬件：使用集成员信息和颜色集通过编译器/微架构合作进行内存子系统优化

• 批准号: 0312892
• 负责人: Soner Onder
• 金额: $ 28万
• 依托单位: Michigan Technological University
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2003
• 资助国家: 美国
• 起止时间: 2003-08-15 至 2007-07-31
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0312892&HistoricalAwards=false
• 关键词: ITR; Exposing; compiler; hardware; Memory

Exposing the compiler to the hardware: Memory Subsystem Optimizations through Compiler/Micro-architecture Cooperation using Set Membership Information and ColorAbstract(Onder)This research proposes to make use of the static knowledge obtained by the compiler in the dynamic decision making of the micro-architecture. In that respect, the compiler exposes compile-time analysis to the micro-architecture fully using set membership information, and the micro-architecture uses this information to make critical scheduling and memory optimization decisions. This approach allows the examination of solutions to the memory wall problem that are impossible to do using a hardware-only or fully compiler-managed solution. Using set membership as a framework, this research will pursue the following problems:1. Cost-effective run-time memory disambiguation of load/store operations to increase the number of parallel memory operations;2. Scalable cache and load/store queue designs that can sustain multiple memory accesses every cycle for wide-issue superscalar processors;3. Novel cache designs formed in cooperation with compiler-generated working-set information to reduce the number of conflict and capacity misses; and,4. Working-set based prefetching techniques to reduce the number of misses and the miss penalty.The proposed research will significantly improve the performance of scientific applications. These applications are at the heart of basic science research, and their performance is crucial for the advancement of many fields of science. This research will also strengthen the synergy between compilers and micro-architectures, and advance the state-of-the-art in information technology.

暴露的编译器的硬件：内存子系统优化，通过编译器/微架构合作使用集成员信息和ColorAbstract（Onder）本研究提出了利用静态知识获得的编译器在动态决策的微架构。在这方面，编译器完全使用集合成员信息向微架构暴露编译时分析，并且微架构使用该信息来做出关键调度和存储器优化决策。这种方法允许检查内存墙问题的解决方案，这些解决方案是使用纯硬件或完全编译器管理的解决方案无法实现的。本研究将以集合隶属度为架构，探讨以下问题：1.成本效益的运行时内存消除歧义的加载/存储操作，以增加并行内存操作的数量;2.可扩展的高速缓存和加载/存储队列设计，可以支持多个存储器访问，每一个周期的广泛发行超标量处理器;3。新颖的高速缓存设计与编译器生成的工作集信息合作形成，以减少冲突和容量未命中的数量;以及，4。基于工作集的预取技术，减少了未命中次数和未命中惩罚，将显著提高科学应用的性能。这些应用是基础科学研究的核心，其性能对于许多科学领域的进步至关重要。该研究还将加强编译器和微体系结构之间的协同作用，并推动信息技术的发展。