ITR: Exposing the compiler to the hardware: Memory Subsystem Optimizations through Compiler/Micro-architecture Cooperation using Set Membership Information and Color Sets

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Exposing the compiler to the hardware: Memory Subsystem Optimizations through Compiler/Micro-architecture Cooperation using Set Membership Information and ColorAbstract(Onder)This research proposes to make use of the static knowledge obtained by the compiler in the dynamic decision making of the micro-architecture. In that respect, the compiler exposes compile-time analysis to the micro-architecture fully using set membership information, and the micro-architecture uses this information to make critical scheduling and memory optimization decisions. This approach allows the examination of solutions to the memory wall problem that are impossible to do using a hardware-only or fully compiler-managed solution. Using set membership as a framework, this research will pursue the following problems:1. Cost-effective run-time memory disambiguation of load/store operations to increase the number of parallel memory operations;2. Scalable cache and load/store queue designs that can sustain multiple memory accesses every cycle for wide-issue superscalar processors;3. Novel cache designs formed in cooperation with compiler-generated working-set information to reduce the number of conflict and capacity misses; and,4. Working-set based prefetching techniques to reduce the number of misses and the miss penalty.The proposed research will significantly improve the performance of scientific applications. These applications are at the heart of basic science research, and their performance is crucial for the advancement of many fields of science. This research will also strengthen the synergy between compilers and micro-architectures, and advance the state-of-the-art in information technology.