SHF: Medium: Collaborative Research: Statically Controlled Asynchronous Lane Execution (SCALE)

支持性能更好的系统有利于应用程序，从运行在移动的设备上的应用程序到运行在数据中心上的大型数据应用程序。大多数应用程序的效率仍然主要受单线程性能的影响。指令级并行（ILP）通过并行执行程序的指令来加速程序，“超标量”处理器实现最大性能。与此同时，能源效率是一个关键的标准，要记住这样的加速发生，这两个是冲突的标准在系统设计。该项目开发了一种静态控制异步通道执行（SCALE）方法，该方法有可能达到或超过传统超标量处理器的性能，同时接近超长指令字（VLIW）处理器的能效。 顾名思义，SCALE方法能够扩展到不同类型和级别的并行性。该项目开发的工具集和设计将以开源形式提供，并将对教育和研究产生影响。SCALE架构和编译器技术将被纳入本科生和研究生课程。SCALE方法支持独立的异步执行通道，其中不同通道中的指令之间的依赖关系由编译器静态识别，以提供通道间同步。提供不同的指令通道允许编译器为不同的执行模式生成代码，以适应应用程序内每个点处可用的并行类型。这些执行模式包括并行指令的显式打包、循环迭代的并行和流水线执行、单程序多数据（SPMD）执行和独立多线程。该奖项反映了NSF的法定使命，并通过使用基金会的智力价值和更广泛的影响审查标准进行评估，被认为值得支持。

Enabling better performing systems benefits applications that span those running on mobile devices to large data applications running on data centers. The efficiency of most applications is still primarily affected by single thread performance. Instruction-level parallelism (ILP) speeds up programs by executing instructions of the program in parallel, with 'superscalar' processors achieving maximum performance. At the same time, energy efficiency is a key criteria to keep in mind as such speedup happens, with these two being conflicting criteria in system design. This project develops a Statically Controlled Asynchronous Lane Execution (SCALE) approach that has the potential to meet or exceed the performance of a traditional superscalar processor while approaching the energy efficiency of a very long instruction word (VLIW) processor. As implied by its name, the SCALE approach has the ability to scale to different types and levels of parallelism. The toolset and designs developed in this project will be available as open-source and will also have an impact on both education and research. The SCALE architectural and compiler techniques will be included in undergraduate and graduate curricula.The SCALE approach supports separate asynchronous execution lanes where dependencies between instructions in different lanes are statically identified by the compiler to provide inter-lane synchronization. Providing distinct lanes of instructions allows the compiler to generate code for different modes of execution to adapt to the type of parallelism that is available at each point within an application. These execution modes include explicit packaging of parallel instructions, parallel and pipelined execution of loop iterations, single program multiple data (SPMD) execution, and independent multi-threading.This award reflects NSF's statutory mission and has been deemed worthy of support through evaluation using the Foundation's intellectual merit and broader impacts review criteria.