SHF: Small: Single Assignment Architecture / Single Assignment Compiler

今天，几乎所有的处理器都采用功能上彼此等同的指令集架构。使用这些传统表示的编译器/微架构合作已经达到了收益递减的地步。因此，该项目研究了单任务程序表示的领域，并通过微体系结构实现直接支持该领域，这是一个可以打破编译器和体系结构之间障碍的关键概念。如果成功，这种新方法将对未来处理器的设计、编译器内部表示的设计以及编译器的后端产生重大影响。它还可以影响在不同粒度下如何利用并行性以及如何执行各种优化。所研究的框架为高性能系统的研究开辟了未知的途径，有助于计算机体系结构和编译器优化的研究。因此，它可以影响依赖于高性能计算的科学和商业的每一个领域。围绕单赋值形式概念的编译器/硬件集成在三个领域有很多好处。首先，在流程同步方面，它提供了消除显式同步需求的机会。其次，在微体系结构领域，指令流的重命名变得非常简单，微体系结构可以实现循环感知，重命名的指令流可以重命名，编译器技术如部分冗余消除或恒定传播可以由微体系结构动态执行。最后，通过与微体系结构共享公共表示，编译器可以专注于它们最擅长的工作。因此，可以有效地执行许多关键优化。在这种范例中，开发新的优化算法成为可能，这些算法将依赖于微架构来使用编译器执行的分析来执行优化。

Today, practically all processors employ instruction set architectures which are functionallyequivalent to each other. Compiler/micro-architecture cooperation using these traditionalrepresentations has already reached the point of diminishing returns. This project thereforeinvestigates the domain of single assignment program representations and direct support of thisdomain through micro-architecture implementation as a key concept that can break the barriersbetween the compilers and architectures. If successful, this new approach can have a significantimpact on the design of future processors, design of compiler internal representations as well asthe back-end of the compilers. It can also affect how parallelism is exploited at variousgranularities and how various optimizations are carried out. The investigated framework can helprevitalize computer architecture and compiler optimization research by opening up unexplored pathsfor research in high-performance systems. Consequently, it can affect every field of science andcommerce which rely on high-performance computation. Compiler/hardware integration around the concept of single-assignment form has many benefitsspanning three fields. First, in the area of process synchronization it provides the opportunity toeliminate the need for explicit synchronization. Second, in the field of micro-architecture renamingof instruction streams becomes substantially simpler, micro-architectures can become loop-aware,renamed instruction streams can be re-renamed and compiler techniques such as partial redundancyelimination or constant propagation can dynamically be performed by the micro-architecture.Finally, the compilers can focus on what they do best by sharing a common representation with themicro-architecture. As a result, many key optimizations can be efficiently performed. Withinthis paradigm, it becomes possible to develop new optimization algorithms which will rely on themicro-architecture to perform the optimization using analysis performed by the compilers.