课题基金 / 基金详情

SHF: Small: Single Assignment Architecture / Single Assignment Compiler

SHF: Small: Single Assignment Architecture / Single Assignment Compiler
SHF:小型:单赋值架构/单赋值编译器
批准号:
1116551
负责人:
Soner Onder
金额:
$15.3万
依托单位国家:
美国
项目类别:
Standard Grant
财政年份:
2011
资助国家:
美国
项目状态:
已结题
起止时间:
2011-08-01 至 2013-07-31

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中文摘要
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英文摘要
Today, practically all processors employ instruction set architectures which are functionallyequivalent to each other. Compiler/micro-architecture cooperation using these traditionalrepresentations has already reached the point of diminishing returns. This project thereforeinvestigates the domain of single assignment program representations and direct support of thisdomain through micro-architecture implementation as a key concept that can break the barriersbetween the compilers and architectures. If successful, this new approach can have a significantimpact on the design of future processors, design of compiler internal representations as well asthe back-end of the compilers. It can also affect how parallelism is exploited at variousgranularities and how various optimizations are carried out. The investigated framework can helprevitalize computer architecture and compiler optimization research by opening up unexplored pathsfor research in high-performance systems. Consequently, it can affect every field of science andcommerce which rely on high-performance computation. Compiler/hardware integration around the concept of single-assignment form has many benefitsspanning three fields. First, in the area of process synchronization it provides the opportunity toeliminate the need for explicit synchronization. Second, in the field of micro-architecture renamingof instruction streams becomes substantially simpler, micro-architectures can become loop-aware,renamed instruction streams can be re-renamed and compiler techniques such as partial redundancyelimination or constant propagation can dynamically be performed by the micro-architecture.Finally, the compilers can focus on what they do best by sharing a common representation with themicro-architecture. As a result, many key optimizations can be efficiently performed. Withinthis paradigm, it becomes possible to develop new optimization algorithms which will rely on themicro-architecture to perform the optimization using analysis performed by the compilers.
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Collaborative Research: SHF: Medium: Vectorized Instruction Space (VIS)
  • 批准号:
    2211353
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $60.0万
  • 财政年份:
    2022
  • 负责人:
    Soner Onder
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IRES: Track I: Collaborative Research: Supporting FSU and MTU Student Research with NTNU Faculty on Automatic Improvement of Application Performance
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    2103105
  • 项目类别:
    Standard Grant
  • 资助金额:
    $15.0万
  • 财政年份:
    2021
  • 负责人:
    Soner Onder
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SHF: Medium: Collaborative Research: Statically Controlled Asynchronous Lane Execution (SCALE)
  • 批准号:
    1901005
  • 项目类别:
    Continuing Grant
  • 资助金额:
    $59.95万
  • 财政年份:
    2019
  • 负责人:
    Soner Onder
  • 依托单位:
FoMR: Collaborative Research: Dependent ILP: Dynamic Hoisting and Eager Scheduling of Dependent Instructions
  • 批准号:
    1823398
  • 项目类别:
    Standard Grant
  • 资助金额:
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    2018
  • 负责人:
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  • 负责人:
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    31972324
  • 项目类别:
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  • 资助金额:
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  • 批准年份:
    2019
  • 负责人:
    高学文
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