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EAGER: Combining Data and Instruction Level Parallelism through Demand Driven Execution of Imperative Programs

EAGER：通过命令式程序的需求驱动执行将数据和指令级并行性相结合

基本信息

批准号：
1450062
负责人：
Soner Onder
金额：
$ 9.79万
依托单位：
Michigan Technological University
依托单位国家：
美国
项目类别：
Standard Grant
财政年份：
2014
资助国家：
美国
起止时间：
2014-09-01 至 2016-08-31
项目状态：
已结题

来源：
https://www.nsf.gov/awardsearch/showAward?AWD_ID=1450062&HistoricalAwards=false
关键词：
EAGER Combining Data Instruction Level

项目摘要

Title: EAGER: Combining Data and Instruction Level Parallelism through Demand Driven Execution of Imperative ProgramsThis project advances a new execution paradigm, namely, demand-driven execution (DDE) of imperative programs. It studies the feasibility of the paradigm by establishing theoretical performance bounds, and identifying its key scalability aspects. The primary intellectual merit of the proposal is the DDE methodology and its use in removing impediments to parallelism due to data flow and control flow. The project's broader significance and importance stems from its impact on the design of future processors, and its synergistic use of compilers and microarchitectures. Processors built using the DDE approach can better utilize computing resources and are energy efficient.The basic idea behind the DDE methodology is to compile C-like programs such that both instruction-level and data-level parallelism can be used through a collaboration between compilers and microarchitectures. The basis for this collaboration is an executable, intermediate program representation known as "Future Gated Single Assignment" (FGSA) form into which a source program is compiled. The FGSA representation not only can be used by an optimizing compiler but also can be used as hardware instructions which can be directly executed by the microarchitecture.

题目：EAGER：通过命令式程序的需求驱动执行结合数据和指令级并行本项目提出了一种新的执行范式，即命令式程序的需求驱动执行（DDE）。通过建立理论性能界限，并确定其关键的可扩展性方面，研究了该范式的可行性。该建议的主要智力优点是DDE方法及其在消除由于数据流和控制流造成的并行性障碍方面的使用。该项目更广泛的意义和重要性源于它对未来处理器设计的影响，以及它对编译器和微架构的协同使用。使用DDE方法构建的处理器可以更好地利用计算资源，并且节能。DDE方法背后的基本思想是编译类c程序，这样就可以通过编译器和微体系结构之间的协作来使用指令级和数据级并行性。这种协作的基础是一种可执行的中间程序表示形式，称为“未来门控单一分配”（FGSA）形式，源程序被编译成这种形式。FGSA表示不仅可以被优化编译器使用，还可以用作硬件指令，可以直接由微架构执行。