SGER: Bridging Nanoelectronics to CMOS

随着CMOS的规模接近尾声，它成为必要的设备范例，可以进行设备集成到更高的密度。在CMOS的规模方面，业界面临的最艰巨的挑战是功率密度。这体现在IC消耗的总功率迅速增加，而单位面积的功率更是不祥之兆。一个有吸引力的路线，以继续在设备的进展是开发一个范例，其中所需的能量是数量级低于可能在CMOS。一个被称为量子点细胞自动机（QCA）的纳米电子学范例拥有这种希望，其中通过使用准绝热时钟，开关能量可以低于kT。此外，时钟QCA单元可以提供用于逻辑电平恢复的真实功率增益。虽然纳米电子学可能是未来电子学的关键技术，但应该认识到，CMOS在缩放结束后很长一段时间内仍将在系统中占有一席之地，并且纳米电子学的实现将必然需要与CMOS接口。CMOS具有大量可以利用的优势，并且应该利用广泛的CMOS基础设施来尽可能平滑地过渡到纳米电子范式。例如，时钟和与外界的接口将由CMOS电路处理，而计算任务将由低功耗纳米电子电路处理。纳米电子学和CMOS的结合将是实现电子系统的一种很好的方式。拟议的项目将探讨纳米电子和CMOS接口的问题。

As the scaling of CMOS nears its end it becomes imperative to a device paradigm that can carry forward device integration to ever-higher densities. The most daunting challenge facing the industry in the scaling of CMOS is power density. This is seen in the rapid increase in the total power dissipated by ICs, and even more ominously in the power per unit area. An attractive route to continue progress in devices is to develop a paradigm where the energy required is orders of magnitude lower than that possible in CMOS. A nanoelectronics paradigm called quantum-dot cellular automata (QCA) holds this promise, where by using quasi-adiabatic clocking the switching energy can be below kT. In addition clocked QCA cells can provide true power gain for logic level restoration. While nanoelectronics is perhaps the key technology for the future of electronics, it should be recognized that CMOS will have a place in systems long after the end of scaling, and implementations of nanoelectronics will necessarily need to interface with CMOS. CMOS has a tremendous number of advantages which can exploited, and the extensive CMOS infrastructure should be leveraged to make the smoothest possible transition to the nanoelectronic paradigm. For example, clocking and interfacing to the outside world would be handled by CMOS circuitry, while computation tasks would be handled by the low-power nanoelectronic circuitry. Combinations of nanoelectronics and CMOS will be an excellent way to implement electronic systems. The proposed project will explore the issues of interfacing nanoelectronics and CMOS.