Programmable Architectures for Low Density Parity Check Codes

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AbstractProgrammable Architectures for Low Density Parity Check CodesVenkatesh Akella Shu LinUniversity of California University of CaliforniaLow-density parity check (LDPC) codes are an important class of error control codes that have superior performance and are gaining widespread use in a diverse range of applications from satellite and space communication to magnetic recording to high data rate optical networks based on optical CDMA. The wide range of applications imply a broad range of requirements in terms of data rates, bit and block error rates, performance, decoding speed and power consumption. This necessitates a systematic methodology to design good LDPC codes and hardware/software platforms to implement them efficiently.Specifically we argue that we need codes and architectures that can (dynamically) adapt to time-varying fluctuations in the physical channel (due to fading, interference etc.) and to the resource constraints of the sender or receiver. The latter is especially important in power critical applications like satellite or space communications. Existing code construction methods and hardware architectures for LDPC codes are typically tailored for one specific code and hence are not capable of adaptation. The goal of this proposal is to address this problem. We propose a systematic methodology for generating a large family of related LDPC codes and a single programmable hardware architecture to encode and decode them efficiently for a varietyof resource and performance constraints. We propose a joint framework for code construction, implementation platform design and methods for optimizing the implementation of the codes on the platform. We propose to investigate runtime selection of appropriate codes and encoding/decoding algorithms based on the resource constraints. The main resource we will be interested in is power consumption of the encoder and decoder.The intellectual merit of the proposed research is two fold. First, we propose to study the trade-offsbetween the rate, decoding complexity both in terms of energy and time and error performance. Second, we target programmable architectures that are suitable for optical networking applications, which require very low bit-error rate and decoding rates in tens of gigabits per second. This will push the limit of programmable architectures and yield new insights into high-speed on-chip programmable interconnection network design.The broader impact of the proposed research would be in the area of reconfigurable VLSI fabrics. Aswe move into process technologies below 65 nanometers, building ASICs (application-specific integrated circuits) is increasingly less viable due to the problems of timing closure and the design cost and design cycle time. There is an immediate need for a new kind of computing fabric that can replace ASICs. The proposed research will be addressing this problem indirectly. Given that efficient interconnect design is the key challenge in high-speed LDPC decoding, if we can come up with an energy efficient FPGA-like VLSI fabric that can support very high data rates for LDPC decoding, then it is likely that, that fabric can be used for other high performance applications that have demanding interconnect requirements.