Programmable Architectures for Low Density Parity Check Codes

摘要低密度奇偶校验码的可编程体系结构加利福尼亚大学的Venkatesh Akella Shu Lin.低密度奇偶校验码(LDPC)是一类重要的差错控制码，具有优异的性能，并在从卫星和空间通信到磁记录到基于光码分多址的高数据速率光网络的各种应用中得到广泛使用。广泛的应用意味着在数据速率、误比特率和误块率、性能、解码速度和功耗方面有广泛的要求。这就需要一种系统的方法来设计好的LDPC码和硬件/软件平台来高效地实现它们。具体地说，我们认为我们需要能够(动态地)适应物理信道(由于衰落、干扰等)中的时变波动的码和结构。以及发送者或接收者的资源限制。后者在卫星或空间通信等电力关键应用中尤为重要。用于LDPC码的现有码构造方法和硬件体系结构通常是为一个特定码定制的，因此不能自适应。这项提议的目标就是解决这个问题。我们提出了一种系统的方法来生成一大类相关的LDPC码，并提出了一种单一的可编程硬件结构来高效地编码和解码它们，以满足各种资源和性能限制。提出了代码构建的联合框架、实现平台的设计以及代码在平台上的优化实现方法。我们建议研究基于资源约束的适当代码的运行时选择和编解码算法。我们感兴趣的主要资源是编解码器的功耗。提出的研究的智力价值是双重的。首先，我们研究了码率、译码复杂度、能量和时间以及误码性能之间的权衡。其次，我们的目标是适用于光网络应用的可编程体系结构，这些应用需要非常低的误码率和数十千兆位每秒的解码率。这将突破可编程体系结构的极限，为高速片上可编程互连网络设计带来新的见解。拟议的研究将在可重构VLSI结构领域产生更广泛的影响。随着我们进入65纳米以下的工艺技术，由于时序关闭以及设计成本和设计周期时间的问题，构建专用集成电路(ASIC)的可行性越来越低。迫切需要一种新的计算结构来取代ASIC。拟议的研究将间接解决这一问题。鉴于高效的互连设计是高速LDPC译码中的关键挑战，如果我们能提出一种能效高的类似于FPGA的VLSI结构，能够支持非常高的LDPC译码数据速率，那么该结构很可能被用于其他有苛刻互连要求的高性能应用中。

AbstractProgrammable Architectures for Low Density Parity Check CodesVenkatesh Akella Shu LinUniversity of California University of CaliforniaLow-density parity check (LDPC) codes are an important class of error control codes that have superior performance and are gaining widespread use in a diverse range of applications from satellite and space communication to magnetic recording to high data rate optical networks based on optical CDMA. The wide range of applications imply a broad range of requirements in terms of data rates, bit and block error rates, performance, decoding speed and power consumption. This necessitates a systematic methodology to design good LDPC codes and hardware/software platforms to implement them efficiently.Specifically we argue that we need codes and architectures that can (dynamically) adapt to time-varying fluctuations in the physical channel (due to fading, interference etc.) and to the resource constraints of the sender or receiver. The latter is especially important in power critical applications like satellite or space communications. Existing code construction methods and hardware architectures for LDPC codes are typically tailored for one specific code and hence are not capable of adaptation. The goal of this proposal is to address this problem. We propose a systematic methodology for generating a large family of related LDPC codes and a single programmable hardware architecture to encode and decode them efficiently for a varietyof resource and performance constraints. We propose a joint framework for code construction, implementation platform design and methods for optimizing the implementation of the codes on the platform. We propose to investigate runtime selection of appropriate codes and encoding/decoding algorithms based on the resource constraints. The main resource we will be interested in is power consumption of the encoder and decoder.The intellectual merit of the proposed research is two fold. First, we propose to study the trade-offsbetween the rate, decoding complexity both in terms of energy and time and error performance. Second, we target programmable architectures that are suitable for optical networking applications, which require very low bit-error rate and decoding rates in tens of gigabits per second. This will push the limit of programmable architectures and yield new insights into high-speed on-chip programmable interconnection network design.The broader impact of the proposed research would be in the area of reconfigurable VLSI fabrics. Aswe move into process technologies below 65 nanometers, building ASICs (application-specific integrated circuits) is increasingly less viable due to the problems of timing closure and the design cost and design cycle time. There is an immediate need for a new kind of computing fabric that can replace ASICs. The proposed research will be addressing this problem indirectly. Given that efficient interconnect design is the key challenge in high-speed LDPC decoding, if we can come up with an energy efficient FPGA-like VLSI fabric that can support very high data rates for LDPC decoding, then it is likely that, that fabric can be used for other high performance applications that have demanding interconnect requirements.