Programmable Architectures for Low Density Parity Check Codes

摘要低密度奇偶校验码（LDPC）是一类重要的错误控制码，具有优越的性能，在卫星和空间通信、磁记录、基于光CDMA的高数据速率光网络等各种应用中得到了广泛的应用。广泛的应用意味着在数据速率、比特和块错误率、性能、解码速度和功耗方面有广泛的要求。这就需要一个系统的方法来设计好的LDPC代码和硬件/软件平台来有效地实现它们。具体来说，我们认为我们需要能够（动态地）适应物理信道中随时间变化的波动（由于衰落、干扰等）以及发送方或接收方的资源约束的代码和架构。后者在卫星或空间通信等功率关键应用中尤为重要。LDPC代码的现有代码构建方法和硬件体系结构通常是为特定代码量身定制的，因此无法适应。本提案的目标就是解决这个问题。我们提出了一种系统的方法，用于生成大量相关的LDPC代码和单个可编程硬件架构，以有效地编码和解码各种资源和性能限制。我们提出了代码构建的联合框架、实现平台设计以及优化代码在平台上实现的方法。我们建议研究基于资源约束的适当代码和编码/解码算法的运行时选择。我们感兴趣的主要资源是编码器和解码器的功耗。这项研究的学术价值有两个方面。首先，我们建议研究速率、解码复杂度（能量和时间）和错误性能之间的权衡。其次，我们的目标是适合于光网络应用的可编程架构，这需要非常低的误码率和每秒几十千兆比特的解码率。这将推动可编程架构的极限，并为高速片上可编程互连网络设计提供新的见解。提议的研究将在可重构VLSI结构领域产生更广泛的影响。随着我们进入65纳米以下的工艺技术，由于时间关闭、设计成本和设计周期时间的问题，构建asic（专用集成电路）越来越不可行。现在迫切需要一种新的计算结构来取代asic。拟议的研究将间接解决这个问题。鉴于高效互连设计是高速LDPC解码的关键挑战，如果我们能够提出一种节能的fpga类VLSI结构，可以支持LDPC解码的非常高的数据速率，那么很可能，该结构可以用于其他高性能应用，要求互连。

AbstractProgrammable Architectures for Low Density Parity Check CodesVenkatesh Akella Shu LinUniversity of California University of CaliforniaLow-density parity check (LDPC) codes are an important class of error control codes that have superior performance and are gaining widespread use in a diverse range of applications from satellite and space communication to magnetic recording to high data rate optical networks based on optical CDMA. The wide range of applications imply a broad range of requirements in terms of data rates, bit and block error rates, performance, decoding speed and power consumption. This necessitates a systematic methodology to design good LDPC codes and hardware/software platforms to implement them efficiently.Specifically we argue that we need codes and architectures that can (dynamically) adapt to time-varying fluctuations in the physical channel (due to fading, interference etc.) and to the resource constraints of the sender or receiver. The latter is especially important in power critical applications like satellite or space communications. Existing code construction methods and hardware architectures for LDPC codes are typically tailored for one specific code and hence are not capable of adaptation. The goal of this proposal is to address this problem. We propose a systematic methodology for generating a large family of related LDPC codes and a single programmable hardware architecture to encode and decode them efficiently for a varietyof resource and performance constraints. We propose a joint framework for code construction, implementation platform design and methods for optimizing the implementation of the codes on the platform. We propose to investigate runtime selection of appropriate codes and encoding/decoding algorithms based on the resource constraints. The main resource we will be interested in is power consumption of the encoder and decoder.The intellectual merit of the proposed research is two fold. First, we propose to study the trade-offsbetween the rate, decoding complexity both in terms of energy and time and error performance. Second, we target programmable architectures that are suitable for optical networking applications, which require very low bit-error rate and decoding rates in tens of gigabits per second. This will push the limit of programmable architectures and yield new insights into high-speed on-chip programmable interconnection network design.The broader impact of the proposed research would be in the area of reconfigurable VLSI fabrics. Aswe move into process technologies below 65 nanometers, building ASICs (application-specific integrated circuits) is increasingly less viable due to the problems of timing closure and the design cost and design cycle time. There is an immediate need for a new kind of computing fabric that can replace ASICs. The proposed research will be addressing this problem indirectly. Given that efficient interconnect design is the key challenge in high-speed LDPC decoding, if we can come up with an energy efficient FPGA-like VLSI fabric that can support very high data rates for LDPC decoding, then it is likely that, that fabric can be used for other high performance applications that have demanding interconnect requirements.