RIA: High-Level Synthesis of Self-Timed Circuits

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Akella This research is focused on developing a systematic approach for high-level synthesis of self-timed circuits. The framework for the research is a set of design tools (SHILPA) that produces macro cell based realizations of circuits from behavioral descriptions. Research problems include the following: 1. techniques for resource sharing based on flow analysis; 2. efficient partitioning of a sequential specification into a set of communicating sequential processes; 3. development of a tool for gate-level realizations of asynchronous circuits in SHILPA; and 4. investigating graphical and VHDL interfaces to SHILPA.