Computational Memory : The computing fabric of the future

计算内存：未来的计算结构

• 批准号: 0541416
• 负责人: Derek Chiou
• 金额: --
• 依托单位: University of Texas at Austin
• 依托单位国家: 美国
• 项目类别: Continuing Grant
• 财政年份: 2006
• 资助国家: 美国
• 起止时间: 2006-05-01 至 2010-04-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0541416&HistoricalAwards=false
• 关键词: Computational; Memory; computing; fabric; future

The traditional way to realize computation in hardware is to devise an algorithm that generates the desired result and then implement that algorithm using combinational logic. Another way to realize computation in hardware is rote memorization, i.e., precompute all the results and store them in memory, a method we call Computational Memory. Our premise is that Computational Memory has properties that are particularly useful as technologies scale to higher densities, but lower reliability and higher performance variability. Memories are very regular and thus very dense, easy to test, and dissipate power much more smoothly than logic. Fault-tolerance on memories and interconnects can, in principle, be systematically implemented using error-correcting codes and/or error detection and recomputation, providing an avenue to address both reliability and performance variability in ultrascaled technology substrates. Such computational memory blocks are cleanly composable, making fault-tolerant designs more tractable with much higher fault coverage. However, even with the high densities that are at our disposal, the exponential memory requirements of a naive implementation of Computational Memory calls into question its practicality. The proposed research will show that this scalability problem can be overcome through the combined use of alternative number systems, coding, caching and architectural techniques. If this work is successful, programmable fabrics based on Computational Memory might emerge as a standard computing framework for the nanotechnology era. This might someday enable inexpensive "computing sticks" that provide portable computing power, along with persistent storage in the form-factor of today?s flash memory.

在硬件上实现计算的传统方法是设计一种算法，产生期望的结果，然后使用组合逻辑实现该算法。在硬件上实现计算的另一种方法是死记硬背，即预先计算所有结果并将其存储在内存中，这种方法我们称为计算内存。我们的前提是，计算内存具有在技术扩展到更高密度时特别有用的特性，但可靠性较低，性能可变性较高。存储器非常规则，因此非常密集，易于测试，并且比逻辑更平稳地耗电。原则上，存储器和互连上的容错可以使用纠错码和/或错误检测和重新计算来系统地实现，为解决超大尺寸技术基板的可靠性和性能可变性提供了一条途径。这样的计算内存块可以清晰地组合，使容错设计更易于处理，并且具有更高的故障覆盖率。然而，即使高密度在我们的处置，指数级内存需求的一个幼稚的实现计算内存的实用性提出了质疑。所提出的研究将表明，这种可扩展性问题可以通过组合使用替代数字系统、编码、缓存和架构技术来克服。如果这项工作取得成功，基于计算存储器的可编程结构可能会成为纳米技术时代的标准计算框架。这可能有一天会使廉价的“计算棒”提供便携式计算能力，以及持久存储在今天的形式因素？S闪存。