Architectures for Silicon Nanoelectronics and Beyond A Workshop to Chart Research Directions

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PROPOSAL : 0541927 DATE : 07/07/2005 ABSTRACT 0541927 Daniel W. Hammerstrom Portland State University The purpose of this proposal is to request funding for NSF to sponsor a workshop. This workshop is being organized by the Collaborative Working Group (CWG) 4 of the SNB (Silicon Nanotechnology and Beyond) Initiative, an agreement between SRC and NSF to increase university research emphasis in this area. The workshop will be held at Portland State University, Portland, Oregon, September 13 and 14. Although NSF will be the primary sponsor, we have also submitted a proposal to ONAMI (Oregon Nano and Microtechnology Institute) for additional funding. The workshop will be by invitation only and will consist of approximately 40 people. The venue will be the University Place, a hotel and conference center owned and operated by Portland State University. Sometimes forgotten, in the quest to design new materials and switches and to get them to work in the laboratory, are the questions of how we will take advantage of nanoelectronic devices for tomorrow's computing. It is likely that nanotechnology will not just be a new kind of device at the bottom of the hierarchy, but that every level in the design stack will be significantly different, including system architectures, algorithms, computational models, computing structures, physical implementations, and devices. In the semiconductor manufacturing, research, and development community, which includes IT, defense technology and communication, it is widely acknowledged that it is important to pursue both extending CMOS technology to its limits and to develop beyond-CMOS technologies, if the semiconductor industry is to sustain its historical exponential improvement in performance/cost over time.