NER/SNB: Implementing Nano-scale, Hierarchical, Distributed Memories with CMOL (Cmos / MOLecular) Circuits
NER/SNB:使用 CMOL(Cmos / MOLeular)电路实现纳米级、分层、分布式存储器
基本信息
- 批准号:0553196
- 负责人:
- 金额:--
- 依托单位:
- 依托单位国家:美国
- 项目类别:Standard Grant
- 财政年份:2005
- 资助国家:美国
- 起止时间:2005-10-01 至 2007-08-31
- 项目状态:已结题
- 来源:
- 关键词:
项目摘要
Abstract:Proposal no: 508533Title: NER/SNB Implementing Nano-scale, Hierarchical, Distributed Memories with CMOL (Cmos / MOLecular) CircuitsPI: Dan Hammerstrom, Co-PI: Jack McCarthyInst: BME Department, OGI School of Science and Engineering Oregon Health & Science UniversityThe project examines the creation of biologically inspired circuit models in a hybrid CMOS / Molecular circuit technology. This research is based on two key assumptions, (1) that sparse, hierarchical, distributed data memories (HDMs) will be an important component of Intelligent Signal Processing, and (2) that the mapping of these models to molecular scale circuitry will be more effective than the mapping of more traditional computation.The HDMs form the primary objective of the overall research program. As computational models, they have very different characteristics from traditional models. They rely more on parallel computation than on raw speed. They are asynchronous and of low precision. And they are fault tolerant. For these reasons molecular scale electronics appear to be a promising computational substrate for these models. To develop HDM technology, we are focusing on a number of important problems:1) Developing network models that demonstrate hierarchical data invariance and abstractions with distributed representations;2) Adding temporal information to the representation;3) Building software systems of multiple HDM components with complementary functional diversity into complex "cognitive" systems;4) Scaling to large networks;5) Studying hardware acceleration;6) Integrating HDMs with existing intelligent computing technologies, in particular digital signal processing and rule-based systems; and7) Applying HDM technology to real world applications.The research performed here focuses on potential hardware acceleration with hybrid micro/nanotechnology. In particular, we will be looking at a hybrid CMOS / Molecular technology, CMOL, and the CrossNet implementation architecture, which are being developed at SUNY Stony Brook by Prof. Likharev and is group.The basic idea of CMOL circuits is to combine the advantages of the currently dominant CMOS technology (including its flexibility and high fabrication yield) with those of single-electron molecular devices with nanometer-scale footprint. The devices would be self-assembled on a pre-fabricated nanowire array fabric, enabling very high function density at acceptable fabrication cost. The CMOL technology seems to be uniquely suited for the implementation of the distributed-crossbar ("CrossNet") family of neuromorphic networks which may allow a very effective implementation of HDMs.
摘要:提案编号:508533标题:NER/SNB使用CMOL(CMOS/分子)电路实现纳米级、层次化、分布式存储器PI:Dan Hammerstrom,Co-PI:Jack McCarth Inst:OGI科学与工程学院BME系俄勒冈健康与科学大学该项目研究了如何在混合的CMOS/分子电路技术中创建生物灵感电路模型。这项研究基于两个关键假设,(1)稀疏、分层、分布式数据存储器(HDMS)将是智能信号处理的重要组成部分,(2)这些模型到分子级电路的映射将比更传统计算的映射更有效。HDMS构成了整个研究计划的主要目标。作为计算模型,它们具有与传统模型非常不同的特点。它们更多地依赖于并行计算,而不是原始速度。它们是异步的,精度不高。而且它们具有容错能力。由于这些原因,分子尺度电子学似乎是这些模型的一种很有前途的计算基质。为了开发HDM技术,我们关注以下几个重要问题:1)开发具有层次数据不变性和分布式表示的抽象的网络模型;2)在表示中添加时间信息;3)将功能多样性互补的多个HDM组件的软件系统构建为复杂的“认知”系统;4)扩展到大型网络;5)研究硬件加速;6)将HDMS与现有的智能计算技术,特别是数字信号处理和基于规则的系统集成;7)将HDM技术应用于现实世界。特别是,我们将研究由Likharev教授在纽约州立大学石溪分校开发的混合CMOS/分子技术CMOL和CrossNet实现体系结构。CMOL电路的基本思想是将目前占主导地位的CMOS技术的优势(包括其灵活性和高制造成品率)与具有纳米尺寸的单电子分子器件的优势相结合。这些器件将在预制的纳米线阵列结构上自组装,以可接受的制造成本实现非常高的功能密度。CMOL技术似乎唯一适合于分布式交叉开关(“CrossNet”)神经形态网络家族的实现,这可能允许非常有效地实现HDMS。
项目成果
期刊论文数量(0)
专著数量(0)
科研奖励数量(0)
会议论文数量(0)
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Daniel Hammerstrom其他文献
Daniel Hammerstrom的其他文献
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{{ truncateString('Daniel Hammerstrom', 18)}}的其他基金
NER/SNB: Implementing Nano-scale, Hierarchical, Distributed Memories with CMOL (Cmos / MOLecular) Circuits
NER/SNB:使用 CMOL(Cmos / MOLeular)电路实现纳米级、分层、分布式存储器
- 批准号:
0508533 - 财政年份:2005
- 资助金额:
-- - 项目类别:
Standard Grant
Architectures for Silicon Nanoelectronics and Beyond A Workshop to Chart Research Directions
硅纳米电子学架构及其他领域绘制研究方向的研讨会
- 批准号:
0541927 - 财政年份:2005
- 资助金额:
-- - 项目类别:
Standard Grant
SGER: Computing with Nano-scale Devices - Looking at Alternative Models
SGER:使用纳米级设备进行计算 - 寻找替代模型
- 批准号:
0408170 - 财政年份:2004
- 资助金额:
-- - 项目类别:
Standard Grant
Research for Mixed Signal Electronic Technologies: A Joint Initiative Between NSF and SRC: Inter-Pulse-Interval Based Mixed Signal Representations
混合信号电子技术研究:NSF 和 SRC 之间的联合倡议:基于脉冲间间隔的混合信号表示
- 批准号:
0120369 - 财政年份:2001
- 资助金额:
-- - 项目类别:
Continuing Grant
Research Initiation - Vlsi (Very Large Scale Integration) Memory Techniques
研究启动 - Vlsi(超大规模集成)内存技术
- 批准号:
7805776 - 财政年份:1978
- 资助金额:
-- - 项目类别:
Standard Grant
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