CAREER: Exploring Heterogeneity Within Chip Multiprocessors

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Future microprocessor chips will contain numerous computational cores, large cache hierarchies, and complex on-chip networks between cores and cache banks. For an application to exploit a processor's peak throughput, it will have to necessarily be composed into many threads. As part of this project, the curriculum at Utah will be revised so that graduating students have the skills to write efficient multi-threaded programs that can harness the compute power in future processors. When multi-threaded applications execute on a chip, different threads and data transfers make varied demands on the hardware in terms of speed, bandwidth, power, reliability, etc. By optimizing specific cores and networks on the chip for different metrics, the hardware can meet the diverse needs of software. A processor that packs in heterogeneous functionalities and device characteristics will likely allow processor throughput to continue its steady rise while not compromising reliability or power-efficiency. This project explores the effect of optimizing on-chip networks for either speed, bandwidth, or power. It also explores the effect of customizing cores to execute the operating system, redundant threads, or speculative threads.