CAREER: Exploring Heterogeneity Within Chip Multiprocessors

未来的微处理器芯片将包含大量的计算核心、大型高速缓存层次结构以及核心和高速缓存组之间的复杂片上网络。对于利用处理器的峰值吞吐量的应用程序，它必须被组合成许多线程。作为该项目的一部分，犹他州的课程将进行修订，使毕业生具备编写高效多线程程序的技能，这些程序可以利用未来处理器的计算能力。当多线程应用程序在芯片上执行时，不同的线程和数据传输对硬件在速度、带宽、功耗、可靠性等方面提出了不同的要求。通过针对不同指标优化芯片上的特定内核和网络，硬件可以满足软件的不同需求。集成了异构功能和设备特性的处理器可能会使处理器吞吐量继续稳步上升，同时不会影响可靠性或能效。该项目探讨了优化片上网络的速度、带宽或功耗的效果。它还探讨了定制内核以执行操作系统、冗余线程或推测线程的效果。

Future microprocessor chips will contain numerous computational cores, large cache hierarchies, and complex on-chip networks between cores and cache banks. For an application to exploit a processor's peak throughput, it will have to necessarily be composed into many threads. As part of this project, the curriculum at Utah will be revised so that graduating students have the skills to write efficient multi-threaded programs that can harness the compute power in future processors. When multi-threaded applications execute on a chip, different threads and data transfers make varied demands on the hardware in terms of speed, bandwidth, power, reliability, etc. By optimizing specific cores and networks on the chip for different metrics, the hardware can meet the diverse needs of software. A processor that packs in heterogeneous functionalities and device characteristics will likely allow processor throughput to continue its steady rise while not compromising reliability or power-efficiency. This project explores the effect of optimizing on-chip networks for either speed, bandwidth, or power. It also explores the effect of customizing cores to execute the operating system, redundant threads, or speculative threads.