Exploiting Fast On-Chip Wires

利用快速片上连线

• 批准号: 0430063
• 负责人: Rajeev Balasubramonian
• 金额: $ 17.5万
• 依托单位: University of Utah
• 依托单位国家: 美国
• 项目类别: Standard Grant
• 财政年份: 2004
• 资助国家: 美国
• 起止时间: 2004-10-15 至 2007-09-30
• 项目状态: 已结题
• 来源: https://www.nsf.gov/awardsearch/showAward?AWD_ID=0430063&HistoricalAwards=false
• 关键词: Exploiting; Fast; Chip; Wires

Exploiting Fast On-Chip WiresAbstractAs VLSI technology scales below 100 nanometer feature sizes, the performance of chip-based systems will be limited by the cost and delay associated with on-chip communication. An important problem facing future microprocessor designers is the efficient movement of data on a chip. The objective of the proposed research is to accurately characterize the cost and performance options for on-chip interconnect, and to develop micro-architectural approaches that use these options efficiently. The expected result is a novel class of hybrid architectures that utilize a small percentage of their wire budget on costly, low-latency long wires to achieve enhanced performance/cost.

随着超大规模集成电路（VLSI）技术在100纳米特征尺寸以下的扩展，基于芯片的系统的性能将受到与片上通信相关的成本和延迟的限制。未来的微处理器设计者面临的一个重要问题是芯片上数据的有效移动。所提出的研究的目的是准确地描述芯片上互连的成本和性能选项，并开发微架构的方法，有效地使用这些选项。预期的结果是一种新型的混合架构，其将其布线预算的一小部分用于昂贵的低延迟长布线，以实现增强的性能/成本。