CPA-CSA: Algorithms and Implementations for Scalable Transactional Memory

点击翻译按钮获取中文摘要

Within a few years, every laptop/desktop/server processor will be amulti-core machine. For an application to perform well, it must beefficiently parallelized to execute on all the cores on the machine.Chip manufacturers must therefore provide architectures thatmake it convenient for programmers to partition an application intomultiple parallel threads. The Transactional Memory (TM) programmingmodel is widely acknowledged to be the best known model forconcurrency: it eliminates deadlocks, provides high performance inthe common case, and greatly simplifies programming. It is receivinggreat attention in research conferences and is also being incorporatedin commercial processors. One of the biggest overheads for such asystem is the communication required between cores to implementtransactional semantics. This overhead significantly impactsperformance and power consumption of future processors. The project explores algorithms to not only reduce the required amount ofcommunication, but also explores mechanisms to reduce the overheadsof communication. The key insight behind the proposed work is that anoptimal on-chip network and transactional memory implementation willemerge by closely studying the interaction between the two. Theinsight developed during this work will lead to better methodologiesto compute an optimal on-chip network. The simulators and toolsdeveloped during the research efforts will also support projects ingraduate and undergraduate courses at the University of Utah.