SHF: Small: Hardware/Software Management of Large Multi-Core Memory Hierarchies

在未来的高性能微处理器中，存储器系统的组织和管理可能是最关键的迫在眉睫的问题。在各种排队结构和长线路中，对内存的访问将导致长时间的延迟和能量开销。根据存储数据的位置，每次访问都会经历不均匀的延迟和能量开销。因此，在内存层次结构中有效地布局数据对于高性能和低功耗至关重要。在本提案中，pi提出了一种综合的硬件/软件策略，用于在具有非均匀延迟和功率的缓存/存储器结构中放置数据。提出了在内存层次结构中经济有效地迁移页面的新机制。这些机制将尝试利用硬件结构、操作系统支持、编译器提示和编译器转换。pi还计划开展更广泛的影响活动，鼓励少数民族参与并加强研究基础设施。

In future high-performance microprocessors, memory system organization and management is perhaps the most critical looming issue. Accesses to memory will incur long delays and energy overheads in various queuing structures and in long wires. Each access will experience non-uniform delay and energy overheads based on the location of the stored data. Efficient layout of data within the memory hierarchy is therefore essential for high performance and low power. In this proposal, the PIs put forth a comprehensive hardware/software strategy for data placement in cache/memory structures with non-uniform delay and power. Novel mechanisms are proposed to cost-effectively migrate pages within the memory hierarchy. These mechanisms will attempt to leverage hardware structures, OS support, compiler hints, and compiler transformations. The PIs also plan to engage in broader impact activities that encourage minority participation and augment research infrastructure.