SHF: Small: Hardware/Software Management of Large Multi-Core Memory Hierarchies

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In future high-performance microprocessors, memory system organization and management is perhaps the most critical looming issue. Accesses to memory will incur long delays and energy overheads in various queuing structures and in long wires. Each access will experience non-uniform delay and energy overheads based on the location of the stored data. Efficient layout of data within the memory hierarchy is therefore essential for high performance and low power. In this proposal, the PIs put forth a comprehensive hardware/software strategy for data placement in cache/memory structures with non-uniform delay and power. Novel mechanisms are proposed to cost-effectively migrate pages within the memory hierarchy. These mechanisms will attempt to leverage hardware structures, OS support, compiler hints, and compiler transformations. The PIs also plan to engage in broader impact activities that encourage minority participation and augment research infrastructure.