SHF: Small: Hardware/Software Management of Large Multi-Core Memory Hierarchies

在未来的高性能微处理器中，存储器系统的组织和管理可能是最关键的问题。 在各种排队结构和长线路中，对存储器的访问将导致长延迟和能量开销。 每个访问将经历基于存储数据的位置的非均匀延迟和能量开销。因此，存储器层次结构内的数据的有效布局对于高性能和低功耗是必不可少的。 在该提案中，PI提出了一个全面的硬件/软件策略，用于在具有非均匀延迟和功率的高速缓存/存储器结构中放置数据。提出了新的机制，以具有成本效益的迁移内存层次结构内的页面。 这些机制将尝试利用硬件结构、操作系统支持、编译器提示和编译器转换。 PI还计划参与更广泛的影响活动，鼓励少数群体参与并扩大研究基础设施。

In future high-performance microprocessors, memory system organization and management is perhaps the most critical looming issue. Accesses to memory will incur long delays and energy overheads in various queuing structures and in long wires. Each access will experience non-uniform delay and energy overheads based on the location of the stored data. Efficient layout of data within the memory hierarchy is therefore essential for high performance and low power. In this proposal, the PIs put forth a comprehensive hardware/software strategy for data placement in cache/memory structures with non-uniform delay and power. Novel mechanisms are proposed to cost-effectively migrate pages within the memory hierarchy. These mechanisms will attempt to leverage hardware structures, OS support, compiler hints, and compiler transformations. The PIs also plan to engage in broader impact activities that encourage minority participation and augment research infrastructure.