CSR: Small: Adaptive Brink-of-Failure Memory Architectures for Future Technologies and Workloads

计算机系统被期望在任何时候都提供正确的输出，因此操作非常保守。不幸的是，这种保守性使重要的性能尚未开发。该项目的目标是通过选择性地放松操作条件，同时从任何由此产生的错误中恢复，来捕获这种未开发的性能。 该项目将调查这样的系统是否特别适合可以容忍偶尔错误的工作负载。 如果成功，该项目将产生技术，可以提高性能，并奠定了基础，为新的算法。计算机系统有慷慨的时间裕度，使他们能够正确的行为，尽管参数变化，电压噪声，温度波动等。该项目试图削减这些时间裕度的内存系统，以安全地推动其性能的极限。存储器控制器可以根据观察到的参数变化来不同地处理存储器系统的不同部分。在未来的技术中，这种能力将更加重要，因为参数变化将要求慷慨的定时裕度。 当存储器控制器在故障边缘运行时，一些错误是不可避免的。 为了科普这些错误，存储系统将增加一个量身定制的纠错系统。 建议的内存系统将是一个非常适合新兴的“近似计算”的工作负载。 除了基于模拟的研究外，该项目还将开发自适应存储器控制器的FPGA原型，并将对现成商品存储器芯片的时序裕度进行实证分析。 该项目跨越系统堆栈的多个层，对硬件、操作系统、编程模型和应用程序进行了关键创新。 拟议的工作将增加社区的参数变化的理解和不同的方法来利用这些变化的优点。 它将有助于创建一类新的有前途的应用程序。 该项目还将支持犹他州大学的教育使命和各种外联工作。

Computer systems are expected to provide correct outputs at all times, and are therefore operated very conservatively. Unfortunately, this conservativeness leaves significant performance untapped. The objective of this project is to capture this untapped performance by selectively relaxing the operating conditions while recovering from any resulting errors. The project will investigate if such a system is especially well suited for workloads that can tolerate occasional errors. If successful, the project will yield technologies that can boost performance and lay the foundations for new kinds of algorithms.Computer systems have generous timing margins so they can behave correctly in spite of parameter variations, voltage noise, temperature fluctuations, etc. The project attempts to shave these timing margins in the memory system to safely push its performance to its limits. The memory controller can handle different parts of the memory system differently, depending on the parameter variation that is observed. Such a capability will be even more vital in future technologies where parameter variations will mandate generous timing margins. When a memory controller operates on the brink of failure, some errors are inevitable. To cope with such errors, the memory system will be augmented with a tailor-made error correction system. The proposed memory system will be an excellent fit for emerging "approximate computing" workloads. In addition to simulation-based studies, the project will develop an FPGA prototype of the adaptive memory controller and will carry out an empirical analysis of timing margins in off-the-shelf commodity memory chips. The project spans multiple layers of the system stack, with key innovations to the hardware, operating system, programming models, and applications. The proposed work will increase the community's understanding of parameter variation and the merits of different approaches to exploit these variations. It will help create a new class of promising applications. The project will also support the educational mission at the University of Utah and various outreach efforts.