CSR: Small: Adaptive Brink-of-Failure Memory Architectures for Future Technologies and Workloads

人们期望计算机系统在任何时候都能提供正确的输出，因此操作起来非常保守。不幸的是，这种保守性没有充分利用显著的性能。该项目的目标是通过选择性地放松操作条件，同时从任何产生的错误中恢复，来捕获未开发的性能。该项目将调查这样的系统是否特别适合能够容忍偶尔错误的工作负载。如果成功，该项目将产生能够提高性能的技术，并为新型算法奠定基础。计算机系统有很大的时间余量，因此它们可以在参数变化、电压噪声、温度波动等情况下正常工作。该项目试图在内存系统中减少这些时间余量，以安全地将其性能推至极限。根据所观察到的参数变化，存储器控制器可以以不同的方式处理存储器系统的不同部分。在未来的技术中，这种能力将更加重要，因为参数的变化将要求大量的时间裕度。当内存控制器在故障的边缘运行时，一些错误是不可避免的。为了处理这种错误，存储器系统将增加一个量身定制的纠错系统。所提出的存储系统将非常适合新兴的“近似计算”工作负载。除了基于仿真的研究外，该项目还将开发自适应存储器控制器的FPGA原型，并将对现货商品存储器芯片的时间裕度进行实证分析。该项目跨越了系统堆栈的多个层，对硬件、操作系统、编程模型和应用程序进行了关键的创新。所提出的工作将增加社区对参数变化的理解以及利用这些变化的不同方法的优点。它将有助于创造一类新的有前途的应用。该项目还将支持犹他大学的教育使命和各种推广工作。

Computer systems are expected to provide correct outputs at all times, and are therefore operated very conservatively. Unfortunately, this conservativeness leaves significant performance untapped. The objective of this project is to capture this untapped performance by selectively relaxing the operating conditions while recovering from any resulting errors. The project will investigate if such a system is especially well suited for workloads that can tolerate occasional errors. If successful, the project will yield technologies that can boost performance and lay the foundations for new kinds of algorithms.Computer systems have generous timing margins so they can behave correctly in spite of parameter variations, voltage noise, temperature fluctuations, etc. The project attempts to shave these timing margins in the memory system to safely push its performance to its limits. The memory controller can handle different parts of the memory system differently, depending on the parameter variation that is observed. Such a capability will be even more vital in future technologies where parameter variations will mandate generous timing margins. When a memory controller operates on the brink of failure, some errors are inevitable. To cope with such errors, the memory system will be augmented with a tailor-made error correction system. The proposed memory system will be an excellent fit for emerging "approximate computing" workloads. In addition to simulation-based studies, the project will develop an FPGA prototype of the adaptive memory controller and will carry out an empirical analysis of timing margins in off-the-shelf commodity memory chips. The project spans multiple layers of the system stack, with key innovations to the hardware, operating system, programming models, and applications. The proposed work will increase the community's understanding of parameter variation and the merits of different approaches to exploit these variations. It will help create a new class of promising applications. The project will also support the educational mission at the University of Utah and various outreach efforts.